• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Custom IC Design
  3. How to exclude subckt ports in certain hierarchy branches...

Stats

  • Replies 1
  • Subscribers 125
  • Views 860
  • Members are here 0

How to exclude subckt ports in certain hierarchy branches?

John Davis
John Davis 2 months ago

This topic is related to this post.
I am able to save device terminal voltage waveforms using save statements such as this:

save * subckt=nfet ports=yes exclude=[b]

How can I exclude subckt instances is certain hierarchy branches?

For example I might want to exclude subckts in top.core<0>, and top.core<1> but save them everywhere else.

  • Sign in to reply
  • Cancel
  • Andrew Beckett
    Andrew Beckett 1 month ago

    I don't think this is possible (at least it's not obvious to me that this might be possible). I would suggest you contact customer support (use the Case menu to submit a support case after logging in) - it might need an enhancement.

    Andrew

    • Cancel
    • Vote Up 0 Vote Down
    • Sign in to reply
    • Cancel

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information