How to apply the instance name used in the schematic to the same mosfet in layout?

This annotation only appears when the stop level is 0, ctrl+F will change the stop level to 0 and you will see the expected behavior.

Thank you, AnalogPNW. THat answers the "how to see it" part. 

But the first part of my original question still begs for an answer: How can I **assign** ....  the instance name.

I am getting clean LVS reports on my verification ... except for the *Instance Name* being wrong. I don't even know how to assign an Instance Name to a layout transistor.

How could something so basic be so elusive?

Kind regards,

Michael A. Banak

This is available in the Edit Instance Properties menu (hotkey 'q' when a device is selected). The attribute name is editable there. If you aren't using layoutXL connectivity with schematic to generate your devices I'd recommend you do so. It will automatically generate the devices with corresponding names from schematics in addition to many other useful features. Also note that the device names cannot necessarily be identical to schematic, if for example you have a multiplier property on a device the automatic generation will add a suffix to each instance (because two instances cannot have the same name).

Thank you for this generous reply!

The precise steps you described are what brought me to this forum. Yes, I tried that. I selected the MOSFET instantiated in the layout, hit "q", and assigned an Instance name to match the schematic. Note this is only a simple inverter, with just one poly stripe for each FET. Simple! Failure to match Layout Instance Name to Schematic Instance name continues. This is true for both the NMOS and PMOS. 

LVS says the Instance names do not match, and I'm looking right at them.

Seeing that I have already done what you described, as the steps to take, I must find out what I am doing wrong within those steps.

The multiplier consideration you described has already haunted me. I am further concerned about mosfets, which share a diffusion, such as the stacked NMOSs in a NAND gate.

I feel a little better, at least, knowing that I anticipated many of your points. I don't feel right pestering you for more at this point. If you have any other ideas, I will take them. I will look closer at your tips, now.

Gratefully,

Michael A. Banak

When you are doing an LVS comparison the instance names do not need to match (there might be an option to enforce that, I haven't looked but if it exists I assume there would be an option to disable it). What you are probably experiencing is that the netlist generated during the comparison alters the names in one or both netlists, it is common in my experience that the layout netlist adds an X in front of each instance name. When you are running the LVS tool there is a field that will specify output netlists from both the schematic and the layout (usually .cdl and .sp files respectively), you can take a look at what you're getting there.

Why, THANK YOU!

Of course, these facts lower my expectations from CADENCE, but I must use what I have. 

I can't wait to check the listings you describe.

Cheers!

MABanak

MB202506119828 said:

Of course, these facts lower my expectations from CADENCE, but I must use what I have

A slightly odd statement. I think all that's happening here is that you're not understanding how the flow works - it's nothing to do with limitations of Virtuoso Schematic Editor or Virtuoso Layout Suite.

First of all, if you are using Virtuoso Layout Suite XL and use the Generate All From Source mechanism to generate the instances, the names will match the schematic (with the proviso that m-factor devices etc may have a different suffix to cope with the one-to-many mapping from schematic to layout, as mentioned earlier).

Secondly, you can change the instance name (as was also mentioned previously) with the edit properties command.

However, the issue you are facing here that the name in LVS (you didn't mention which LVS tool you are using) may be undefined on the layout side. That's usually because most LVS tools use Stream format (a.k.a. GDSII) which has no concept of an instance name. You get instances, but there's no name stored in the format. As a result, LVS won't see the name of the instance from the layout. Even if the instance name had been there for the transistors, LVS tools (usually, unless using some kind of black-boxing) recognize the devices by the interaction of the polygons in the layout - i.e. they will recognize the MOS device by the poly crossing diffusion and then construct and measure a device from that - the fact that it was an instance in the first place generally won't affect things - so it's identifying devices from the shapes. A multi-finger device would be recognised as multiple parallel transistors and the comparison stage will compare these devices with equivalent from the schematic.

Regards,

Andrew

Thank you so very much for that generous reply. I wish there was some way to repay all these courtesies I am receiving.

Looks like I owe someone an apology. In my board layout world, comparing layout to the schematic is tight and unambiguous.

I have designed many IC's, but the CADENCE system is new to me. I must keep in mind the nuances you described.

I didn't know there were multiple versions of LVS. But, it's good to know that I anticipated the association of a particular MOSFET with the Poly Crossing. 

I'll keep trying, and thanks, again.

Michael B

I don't think GDS -> netlist is unique to Cadence. I've used a couple of other design tools that have a similar flow. Cadence has their own in house LVS tool (Pegasus) but there are many third party vendors that also provide additional options that work within the Cadence environment. The most common third party LVS tool is Calibre which is from Siemens EDA (formerly Mentor Graphics).

Again, my sincerest thanks to the correspondents, here.

It appears that my LVS, and a few other downstream problems, are caused by the CADENCE installation, which I am using at this institution, not being properly licensed. It appears to be server-specific. 

But this means that future inquiries are on hold until we fix this.

Most gratefully,

Michael B