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Problems with genvar and nested for loops in verilog-A after updating the Cadence tools

Hi everyone,

I recently updated several Cadence tools due to end-of-life notices for the versions we were using. After the upgrade, Virtuoso and Spectre launch without issue, but I’m now encountering a problem when simulating Verilog-A models — specifically with structural code using genvar and for loops.

The model in question is used to generate parametrized ring oscillator structures from a previously designed inverter module (RDUC_INV_V2). The structure chains a configurable number of inverters (N_stage), and then stacks delay lines to form a 2D array. Here is a picture as an example:

The code has run successfully in the past, but under the new tool versions it consistently fails with the following error:

-----------------------------------------------------------------

Error found by spectre during AHDL compile.
ERROR (VACOMP-2245): Internal Compiling Error: node name "intern[0]" not
found (addr = 280281600).

Internal error found in spectre during AHDL compile, during generation of ADE
DPLs.

FATAL (SPECTRE-18): Segmentation fault. Encountered a critical error during
simulation.

****LIBRARIES****
spectre/bin/64bit/spectre [0x400000]
/lib64/libpthread.so.0 [0x7fb15c526000]
/lib64/libc.so.6 [0x7fb15b99b000]

-----------------------------------------------------------------

After some debugging we suspect the issue is with how genvar is used in nested for loops to instantiate inverters and assign signals. The rest of the Verilog-A code — including different simple structural code — still compiles and simulates correctly. This points to a syntax compatibility issue and not a tool issue.

This is the code:
-----------------------------------------------------------------

// VerilogA for VerilogA_layout_ring_osc, VerilogA_Layout_test, veriloga

`include "constants.vams"
`include "disciplines.vams"

module VerilogA_RDUC_V2_Power_test(VDD, VSS, out, INV_IN, INV_OUT, intern);

parameter integer N_stage = 3;
parameter integer tech = 1;
parameter integer test = 1;
parameter integer stacked = 1 from [1:500];
parameter integer turned_on = 1 from [0:500];

inout VDD, VSS;
input INV_IN;
output INV_OUT, out;
output [0:110] intern;

electrical out, VDD, VSS, INV_IN, INV_OUT;
electrical [0:110] intern;
electrical [2:0] phi;
electrical [stacked-1:0] EN;

// initialize the instances before the generate blocks

RDUC_INV_V2 I4(.VDD(VDD),.VSS(VSS),.IN(INV_IN),.OUT(INV_OUT),.EN(VDD));
RDUC_INV_V2_HVT I5(.VDD(VDD),.VSS(VSS),.IN(INV_IN),.OUT(INV_OUT),.EN(VDD));
RDUC_INV_V2_LVT I6(.VDD(VDD),.VSS(VSS),.IN(INV_IN),.OUT(INV_OUT),.EN(VDD));
RDUC_INV_V2_R_big I7(.VDD(VDD),.VSS(VSS),.IN(INV_IN),.OUT(INV_OUT),.EN(VDD));
RDUC_INV_V2_R_small I8(.VDD(VDD),.VSS(VSS),.IN(INV_IN),.OUT(INV_OUT),.EN(VDD));

if (tech == 1) begin
if (N_stage != 1 && N_stage%2 == 1 && N_stage <= 26)begin
genvar stack;
for (stack = stacked-1; stack>=0; stack = stack -1) begin // for loop to generate the correct amount of stacked delay lines
genvar i;
for (i = 1;i<= N_stage-1;i=i+1) begin // for loop to generate the delay line with the correct amount of inverters
RDUC_INV_V2 I0(.VDD(VDD),.VSS(VSS),.IN(intern[i]),.OUT(intern[i+1]),.EN(EN[stack]));
end
genvar j;
for(j=N_stage;j<=N_stage;j=j+1) begin
RDUC_INV_V2 I1(.VDD(VDD),.VSS(VSS),.IN(intern[j]),.OUT(out),.EN(EN[stack])); // connecting the output of the last inverter to the output of the block
end
end

// Enable the correct amount of inverters to get frequency tuning

genvar l;
for (l = stacked-1; l>=stacked-turned_on; l = l -1) begin
analog V(EN[l], VSS) <+ V(VDD, VSS);
end

genvar m;
for (m = stacked-turned_on-1; m>=0; m = m -1) begin
analog V(EN[m], VSS) <+ 0;
end

if (test == 1) begin
analog V(out,intern[1]) <+0; // connecting the output to the first signal to create the feedback loop of the RO
end
end

end
endmodule

-----------------------------------------------------------------

I’ve also tried restructuring the module to use the updated port syntax and a generate block explicitly, but the issue remains.

Has anyone run into this kind of issue with newer versions or seen changes in how structural Verilog-A is parsed? I'd appreciate suggestions on how to refactor the code for compatibility, or whether this is something that requires support intervention.

Thank you in advance!

I've included the previous and updated tool versions, both versions of the tested Verilog-A code, and the full error message in the attachments.

Fullscreen Full_error_message.txt Download

Reading file: 
        /users/advise/etackx/design/ring_osc/VerilogA_test/VerilogA_RDUC_V2_Power_test/veriloga/veriloga.va
Reading file: 
        /esat/micas-data/software/Cadence/spectre_23.10.242/tools.lnx86/spectre/etc/ahdl/constants.vams
Reading file: 
        /esat/micas-data/software/Cadence/spectre_23.10.242/tools.lnx86/spectre/etc/ahdl/disciplines.vams

Error found by spectre during AHDL compile.
    ERROR (VACOMP-2245): Internal Compiling Error: node name "intern[0]" not
        found (addr = 254626048).
        Please send the netlist, log files, behavioral model files, and any
        other information that can help identify the problem to
        support@cadence.com.
Internal error found in spectre during AHDL compile, during generation of ADE
        DPLs.
    FATAL (SPECTRE-18): Segmentation fault. Encountered a critical error during
        simulation. Run `mmsimpack' (see mmsimpack -h for detailed usage
        information) to package the netlist and log files as a compressed tar
        file. Then, contact your Cadence representative or submit a service
        request via Cadence Online Support, including the tar file and any
        other information that could help identify the problem.Version 23.1.0.242.isr1 64bit -- 7 Sep 2023

****ASSERTION STACK****
	0x6e01ecc
	0x936c1c
	0x937746
	0x7f36ae0d3990
	0x61a12f8
	0x614a45f
	0x614a544
	0x614a7b7
	0x6150698
	0x62ba752
	0x601414a
	0x8f62b8
	0x8ca412
	0x8ff39c
	0x81ad09
	0x82483a
	0x82644c
	0x78d519
	0x7f36ad5707e5
	0x80c134

****LIBRARIES****
	spectre/bin/64bit/spectre [0x400000]
	/lib64/libpthread.so.0 [0x7f36ae0c1000]
	/lib64/libc.so.6 [0x7f36ad536000]

Fullscreen Previous_and_new_tools.txt Download

These are the previously used tools: 

#!/bin/bash


source /users/micas/micas/design/scripts/ic_6.1.8.170.rc

source /users/micas/micas/design/scripts/calibre_2019.4.rc

source /users/micas/micas/design/scripts/spectre_20.10.rc

source /users/micas/micas/design/scripts/ads_2020.u1.rc

source /users/micas/micas/design/scripts/incisiv_15.20.058.rc



These are the new tools: 

#!/bin/bash


source /users/micas/micas/design/scripts/ic_6.1.8.170.rc

#source /users/micas/micas/design/scripts/calibre_2020.2_35.23.rc
export MGC_HOME=/esat/micas-data/software/Mentor/calibre_2020.3/aoi
export PATH=$PATH:$MGC_HOME/bin
export MGLS_LICENSE_FILE=1717@licserv


source ~micasusr/design/scripts/ic_23.10.020.rc

source ~micasusr/design/scripts/calibre_2023.1_18.8.rc

source ~micasusr/design/scripts/spectre_23.10.242.rc

#source /users/micas/micas/design/scripts/spectre_20.10.rc

source /users/micas/micas/design/scripts/ads_2020.u1.rc

#source /users/micas/micas/design/scripts/xcelium_19.03.rc

export CDS_XCELIUM=/esat/micas-data/software/Cadence/xcelium_20.09
export PATH="${PATH}:${CDS_XCELIUM}/bin:${CDS_XCELIUM}/tools/bin:${CDS_XCELIUM}/tools/cdsgcc/gcc/bin"

Fullscreen Code_V2.txt Download

// VerilogA for VerilogA_layout_ring_osc, VerilogA_Layout_test, veriloga

`include "constants.vams"
`include "disciplines.vams"

module VerilogA_RDUC_V2_Power_test_V2 (
inout electrical VDD,
inout electrical VSS,
input electrical INV_IN,
output electrical INV_OUT,
output electrical out,
output electrical [0:110] intern
);

parameter integer N_stage = 3;
parameter integer tech = 1;
parameter integer test = 1;
parameter integer stacked = 1 from [1:500];
parameter integer turned_on = 1 from [0:500];

electrical [2:0] phi;
electrical [stacked-1:0] EN;


// initialize the instances before the generate blocks
RDUC_INV_V2 I4(.VDD(VDD),.VSS(VSS),.IN(INV_IN),.OUT(INV_OUT),.EN(VDD));
RDUC_INV_V2_HVT I5(.VDD(VDD),.VSS(VSS),.IN(INV_IN),.OUT(INV_OUT),.EN(VDD));
RDUC_INV_V2_LVT I6(.VDD(VDD),.VSS(VSS),.IN(INV_IN),.OUT(INV_OUT),.EN(VDD));
RDUC_INV_V2_R_big I7(.VDD(VDD),.VSS(VSS),.IN(INV_IN),.OUT(INV_OUT),.EN(VDD));
RDUC_INV_V2_R_small I8(.VDD(VDD),.VSS(VSS),.IN(INV_IN),.OUT(INV_OUT),.EN(VDD));

genvar stack; 
genvar i; 
genvar j;
genvar l;
genvar m;

generate 
if (tech == 1) begin
	if (N_stage != 1 && N_stage%2 == 1 && N_stage <= 26)begin         
		for (stack = stacked-1; stack>=0; stack = stack -1) begin        // for loop to generate the correct amount of stacked delay lines
			for (i = 1;i<= N_stage-1;i=i+1) begin                    // for loop to generate the delay line with the correct amount of inverters
				RDUC_INV_V2 I0(.VDD(VDD),.VSS(VSS),.IN(intern[i]),.OUT(intern[i+1]),.EN(EN[stack]));
			end		
			for(j=N_stage;j<=N_stage;j=j+1) begin
				RDUC_INV_V2 I1(.VDD(VDD),.VSS(VSS),.IN(intern[j]),.OUT(out),.EN(EN[stack]));       // connecting the output of the last inverter to the output of the block    
			end 
		end

		// Enable the correct amount of inverters to get frequency tuning
		for (l = stacked-1; l>=stacked-turned_on; l = l -1) begin
			analog V(EN[l], VSS) <+ V(VDD, VSS);
		end

		for (m = stacked-turned_on-1; m>=0; m = m -1) begin
			analog V(EN[m], VSS) <+ 0;
		end

		if (test == 1) begin
			analog V(out,intern[1]) <+0;		// connecting the output to the first signal to create the feedback loop of the RO
		end
	end
end
endgenerate
endmodule

Fullscreen Code_V1.txt Download

// VerilogA for VerilogA_layout_ring_osc, VerilogA_Layout_test, veriloga

`include "constants.vams"
`include "disciplines.vams"


module VerilogA_RDUC_V2_Power_test(VDD, VSS, out, INV_IN, INV_OUT, intern);

parameter integer N_stage = 3;
parameter integer tech = 1;
parameter integer test = 1;
parameter integer stacked = 1 from [1:500];
parameter integer turned_on = 1 from [0:500];

inout VDD, VSS;
input INV_IN;
output INV_OUT, out;
output [0:110] intern;

electrical out, VDD, VSS, INV_IN, INV_OUT;
electrical [0:110] intern;
electrical [2:0] phi;
electrical [stacked-1:0] EN;


// initialize the instances before the generate blocks
RDUC_INV_V2 I4(.VDD(VDD),.VSS(VSS),.IN(INV_IN),.OUT(INV_OUT),.EN(VDD));
RDUC_INV_V2_HVT I5(.VDD(VDD),.VSS(VSS),.IN(INV_IN),.OUT(INV_OUT),.EN(VDD));
RDUC_INV_V2_LVT I6(.VDD(VDD),.VSS(VSS),.IN(INV_IN),.OUT(INV_OUT),.EN(VDD));
RDUC_INV_V2_R_big I7(.VDD(VDD),.VSS(VSS),.IN(INV_IN),.OUT(INV_OUT),.EN(VDD));
RDUC_INV_V2_R_small I8(.VDD(VDD),.VSS(VSS),.IN(INV_IN),.OUT(INV_OUT),.EN(VDD));

if (tech == 1) begin
    if (N_stage != 1 && N_stage%2 == 1 && N_stage <= 26)begin    
        genvar stack;
        for (stack = stacked-1; stack>=0; stack = stack -1) begin     // for loop to generate the correct amount of stacked delay lines
            genvar i;
            for (i = 1;i<= N_stage-1;i=i+1) begin                     // for loop to generate the delay line with the correct amount of inverters
                RDUC_INV_V2 I0(.VDD(VDD),.VSS(VSS),.IN(intern[i]),.OUT(intern[i+1]),.EN(EN[stack]));
            end
            genvar j;
            for(j=N_stage;j<=N_stage;j=j+1) begin
                RDUC_INV_V2 I1(.VDD(VDD),.VSS(VSS),.IN(intern[j]),.OUT(out),.EN(EN[stack]));      // connecting the output of the last inverter to the output of the block

            end
        end

	// Enable the correct amount of inverters to get frequency tuning
        genvar l;
        for (l = stacked-1; l>=stacked-turned_on; l = l -1) begin
            analog V(EN[l], VSS) <+ V(VDD, VSS);
        end

        genvar m;
        for (m = stacked-turned_on-1; m>=0; m = m -1) begin
             analog V(EN[m], VSS) <+ 0;
        end

        if (test == 1) begin
            analog V(out,intern[1]) <+0; // connecting the output to the first signal to create the feedback loop of the RO
        end
    end


end
endmodule

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