Automatic routing --> All nets in Layout GXL of Cadence Virtuoso

Hello everyone,

I am using Cadence Virtuoso IC6.18.120

I am trying to do automatic layout for a schematic design of a LNA circuit (including 2 nmos_rf, 3 inductors spiral_std_mu_z, 2 capacitors mimcap_um_rf from the tsmc65 PDK). When I do the automatic routing with all the instances and pins generated from the schematic, there are still incomplete nets (I double-checked by using Connectivity --> Incomplete nets --> Show/Hide all) on the terminals of the inductor and capacitors. 

I tried with several simple circuits: nmos and inductor and a few pins, nmos and capacitors and inverter, they all have incomplete nets when doing automatic routing --> all nets. 

Do you have any suggestion for this problem? How can I solve it?

Thank you very much!