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verilog Syntax errors not highlighted in text editor

JavierC

Hello,

I am testing a fresh install of Cadence Virtuoso IC23.1-64b.ISR2.29.

I created a new cell view of type Verilog and added some lines of code including syntax errors. Then, I go to File - Extract and the following shows in the CIW:

Library Manager new cellview request for cell "ONEKEY_digital_sims SPI_master".

(TE-4223): Extracting cellview 'ONEKEY_digital_sims SPI_master functional' ...

ERROR (SHDB-11): Failed to parse the verilog module for design unit (ONEKEY_digital_sims SPI_master functional). Either there are compilation

errors or cellview is not writable or verilog module does not exist in the file.

ERROR (TI-7001): Cannot load the connectivity information for cellview 'ONEKEY_digital_sims/SPI_master/functional' in text file

'/HDD/HDD_Documents/PROJECTS/ONEKEY/CADENCE/LIBS/ONEKEY_digital_sims/SPI_master/functional/verilog.v'.

Verilog *E,PARSEERR: Either there are parsing errors or cell SPI_master is not

found in /HDD/HDD_Documents/PROJECTS/ONEKEY/CADENCE/LIBS/ONEKEY_digital_sims/SPI_master/functional/verilog.v

file.

When I go to View - Parser Log File, the following shows:

========================================================================================================
HDL IMPORT QUICK STATUS REPORT
========================================================================================================
HDL SETUP MODE : 0 - IMPROVED LEGACY FLOW
========================================================================================================
HDL SETUP STATUS : SUCCESS
========================================================================================================
cds.lib USED : "/HDD/HDD_Documents/PROJECTS/ONEKEY/CADENCE/cds.lib"
========================================================================================================
COMPILER OPTIONS : ""
========================================================================================================
PCDB DM CHECKS : SUCCESS
========================================================================================================
PCDB UPDATE REQUIRED : YES
========================================================================================================
IMPORT CONFIGURATION : CHECK BELOW SETTINGS
: generateShadow(true)
: enableBlackBox(false)
: enableSpecificUnit(true)
: updateCDF(true)
========================================================================================================
OVERALL IMPORT STATUS : FAILED
=======================================================================================================

Could anybody point me towards a solution? Thanks in advance.

JC

Parents

  • Hi,

    I understand that the log contains no information about the syntax errors in your code. This should be written out before 'HDL IMPORT QUICK STATUS REPORT' section. The built-in text editor highlights the text with incorrect syntax as well.

    There can be a few reasons for the behaviour you see -

    1. Not enough disk space as the message states

    2. Switching to a newer version might help. With your current version, please set the below in CIW and re-run extract -

    vmsEnableRapidImport=nil

    Saloni

  • in reply to Saloni Chhabra

    Hello Saloni,

    You are correct, the log contains no info about the syntax errors. And neither does the text editor.

    Which message is showing that there is not enough disk space? There should be more than enough (>800 GB).

    I tested your command and the errors still not show in the text. However, a new error shows in the CIW:

    (TE-4223): Extracting cellview 'ONEKEY_digital_sims verilog_dummy functional' ...

    *Error* _gets: argument #1 should be an I/O port (type template = "p") - nil

    *WARNING* (TE-1308): Failed to perform syntax check for cellview 'ONEKEY_digital_sims verilog_dummy functional'.

    *WARNING* (TE-1312): Compilation errors or warnings have been detected in the HDL file for cellview 'ONEKEY_digital_sims verilog_dummy functional'. To view the parse log for details, choose 'Parser Log File' from the 'View' menu.

    *WARNING* (TE-4309): Extract failed for cellview 'ONEKEY_digital_sims verilog_dummy functional'

    I am testing now with a very simple verilog code, no syntax errors here:

    //Verilog HDL for "ONEKEY_digital_sims", "verilog_dummy" "functional"
    module verilog_dummy (input wire in, output wire out );
    assign out = in;
    endmodule

    Is there a way to check if the verilog parser is working? I am afraid this has to do with the installation (it works well in IC6.1.7 and IC6.1.8).

    Thanks again,

    JC

  • in reply to JavierC

    Hello again,

    I have realised that, whenever I extract the verilog module, an error shows in the linux console as well:

    sh: line 1: /eda/cadence/2023-24/RHELx86/XCELIUM_23.03.007/tools/bin/xrun: No such file or directory

    So probably the problem is related to the install. I will investigate further.

    Regards,

    JC

  • in reply to JavierC

    Yes, I just managed to reproduce your issue by removing Xcelium from the path. Please fix your Xcelium installation (or point to another valid installation) and that will resolve text check&save errors as well.

    Before you launch Virtuoso, please run 'xrun -version' on the command-line (terminal). It should return a version as below (mine is newer than 23.03) -

    TOOL: xrun 24.09-s010

    Regards,

    Saloni

Reply
  • in reply to JavierC

    Yes, I just managed to reproduce your issue by removing Xcelium from the path. Please fix your Xcelium installation (or point to another valid installation) and that will resolve text check&save errors as well.

    Before you launch Virtuoso, please run 'xrun -version' on the command-line (terminal). It should return a version as below (mine is newer than 23.03) -

    TOOL: xrun 24.09-s010

    Regards,

    Saloni

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