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How to greate guard ring for Cadence GPDK FinFet?

hesaliveJim

Using the Cadence Generic (cds_ff_mpt 1.1) PDK I'm not sure how to make a  tap for the n device and the p devices. This I need to connect to the bulk to the substrate for the n channel ect.

The mpp Guard ring seems inactive in Cadence XL and the fluid Guard ring seems to want to create some peculiar structure with dummies in it. Also I cannot get it to stretch. These mpp and fluid tools normally make easy work of biasing the mosfet source properly.

Some pointer to get going would be good say for n1lvt and p1lvt mosfets or any for that matter.

the image above is a good example of a layout disaster!

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  • That structure for the guard ring is typical of what you see in FinFET technologies. The simple guard rings used in larger nodes won't work - which is why there's no MPP template (it wouldn't make sense). It is stretchable (for me) - the path that is highlighted in your picture (with the dashed lines) should be stretchable with the normal stretch command - start stretch (with nothing selected) and then click on the centre of that path on the edge you wish to select (or use F4 and pre-select the edges to stretch).

    As for taps, use the Create->Via and create subTap or nwellTap.

    Note, I don't really have any experience of doing layout in this specific generic technology, so I can't comment too much about it - maybe others can.

    Andrew

  • in reply to Andrew Beckett

    Andrew yes I can now stretch following what you said; thank you for getting me started with the subTap and nwellTap.

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