All pins on schematics unconnected to their attached wires when importing EDIF from Siemens,

Hi. I am currently moving some design schematics over from Siemens EDA using the EDIF import functionality (Virtuoso 25.1). While the schematics import fine themselves, there appears to be an issue with every single input/output pin in every single schematic. While they're connected to the pin physically with a wire, when I press check and save, it tells me that they are floating. The only fix I've found is copying the pin, deleting the old one, and replacing it with the copied version. That removes the floating net warning when checking and saving. Unfortunately this is extremely time consuming for multiple different libraries. I want to know if there's a way to refresh connectivity automatically or force it to recognize that there IS a pin connected to that net. I also face the issue where the wires appear on top of the pins of device symbols instead of under/connected.  Thank you!