LUT implementation using VerilogA code In Cadence Virtuoso

Hi. I am trying to read the LUT_2D.tbl file which i want to read through Verilog A code. Two parameters are acting as an input Phi and V2_bias respectively. I want to input these two parameters and it should find for the values the corresponding Rs,Z1_Re,Z1_Im,Z2_Re,Z2_Im,Z3_Re,Z3_Im from the look up table and output it as a voltage which i am providing as an input to another verilog A block as an input. I don't know what is the issue with my verilog A code cause it's not working and prompting me the following error.

Error:

Fatal error found by spectre during initial setup.
FATAL (ASL-4407): "/home/users/Zulfiqar.Ali/project/Design_cadence/tsmc65_GP/ws/Custom_ahdlib/LUT_block/veriloga/veriloga.va" 22: I40: $table_model failed: Encountered extra control character `R' in control string `Rs'. Correct the problem and try again.

Here is my Verilog A code 

`include "constants.h"
`include "discipline.h"

module LUT_block(Rs_out, X1_out, X2_out, X3_out);

// === Outputs ===
output Rs_out, X1_out, X2_out, X3_out;
electrical Rs_out, X1_out, X2_out, X3_out;

// === Parameters ===
parameter real phi = 90.0 from [5:270]; // phase in degrees
parameter real V2_bias = 0.5 from [0.1:1.75]; // V2 bias value

// Full path to LUT file
parameter string LUT_FILE = "/home/users/Zulfiqar.Ali/project/Design_cadence/tsmc65_GP/ws/LUT_Table/LUT_2D.tbl";

// === Local reals ===
real Rs_val, X1_val, X2_val, X3_val;

analog begin
// Direct lookups using phi and V2_bias
Rs_val = $table_model(phi, V2_bias, LUT_FILE, "Rs");
X1_val = $table_model(phi, V2_bias, LUT_FILE, "Z1_Im");
X2_val = $table_model(phi, V2_bias, LUT_FILE, "Z2_Im");
X3_val = $table_model(phi, V2_bias, LUT_FILE, "Z3_Im");

// Drive outputs as voltages equal to looked-up values
V(Rs_out) <+ Rs_val;
V(X1_out) <+ X1_val;
V(X2_out) <+ X2_val;
V(X3_out) <+ X3_val;
end
endmodule