Simulating an Encrypted Netlist

Hopefully the encrypted netlist has just the contents of the subckt encrypted and not the subckt name and pins - that's going to be easier (as that way you know the subckt name and pin order).

In general the approach would be one of those covered in this article: FAQ: How to include a subcircuit (netlist) into a schematic and simulate in ADE

Andrew

Hi Andrew, Thanks for sending the link.

To test drive things I started with a simple un-encrypted netlist.  I decided to use Method 3, however when running the test bench in ADE, I get the belowerror:

 ERROR (SFE-2391): Modelname parameter value for instance I4 has an invalid data type specification

I noticed that when running the sim, the ADE "Design Variables" window adds the "Model" name as a variable. I would like to add a screenshot of what I am seeing but for some reason the system wont allow me to. (i can email the screenshot to you directly if that would help)

I must mention, the un-encrypted netlist I am using has 3 sub circuits. A top level sub-ckt and 2 other sub-ckt that the top-level calls. Would a multi-sub circuit netlist change how I do things?

I think I have done everything correctly - any recommendations on how to work out where I am slipping up?

In the CDF, I would suggest setting the ParseAsCEL and ParseAsNumber to both be "no" or if in IC23.1 set the Evaluation Mode to "literal" for the model parameter. I'd also (in the base CDF) set the default value to the name of the subckt (so you don't have to enter it for every instance).

I think the design variables issue is a consequence of the parseAs settings - it's made it into a design variable, and then it's not netlisted correctly.

Having made the changes above, remove any extraneous design variables, and do a Simulation->Netlist->Recreate. Try simulating - if it fails still, give the error and also the instance line in the netlist for the block in question.

SC202412036016 said:

I must mention, the un-encrypted netlist I am using has 3 sub circuits. A top level sub-ckt and 2 other sub-ckt that the top-level calls. Would a multi-sub circuit netlist change how I do things?

No, that doesn't matter. You are just ensuring that you define the interface from your schematic to the top-level subckt; anything lower level doesn't need to be visible in Virtuoso.

Andrew