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  3. new DRC rule(s) added to new(er) gpdk045 versions?

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new DRC rule(s) added to new(er) gpdk045 versions?

GS202507021424
GS202507021424 3 hours ago

I have developed a cell (schematic and layout) a while ago, using gpdk045 v.2.0, and the DRC came back squeaky clean.

After having updated my Cadence tooling and gpdk045 version (now using v.6.0), my layout is running afoul of the following rule (in `gpdk045_v_6_0/assura/assuraDRC.rul`):

metx1_a=drcDenseLineEnd(Metal1 sep < 0.08 endLength(0.06 0.09) legLength(.10) endExt(.025) legExt(0.025))
errorLayer(metx1_a "METAL1.SP.3: Min End of Line Spacing >= 0.08")

This rule was not present in gpdk045_v_2_0, and I have a few questions:

  1. what is the general significance of DRC rules being added in subsequent releases of a PDK? I.e., how come "it wasn't a problem" in v.2.0, but is "suddenly an issue" in v.6.0 ? Slight smile
  2. is this a "soft" rule that can be ignored with relatively little risk, or a "hard" one that one had better satisfy (in general, assuming a fabricatable PDK)?

Thanks in advance for any insight!

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  • Andrew Beckett
    Andrew Beckett 2 hours ago

    First of all, remember that this is not a real technology. It's a sample technology used to demonstrate typical features of a 45nm CMOS technology.

    The rule was (probably) added as it's typical in many 45nm technologies to have end-of-line spacing rules like this. There is of course no "risk" because it's not real. In a real technology, it would be something you should fix. Such rules might get added in real technology rule files if a yield problem was found in manufacturing (which is a little tricky in a fictitious technology!)

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