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Unmatched schematic pin label

RV202509139743

Hi,

I am doing LVS with PVS 241 at the top level of a chip for the tapeout with IO Ring. I have several VDDs (VDDA, VDDB, etc.), all the same voltage. I have 4 "power domains" that are separated by power-cuts. I included one vdd! in the top schematic and a gnd!

One of the errors that I am having is :

Unmatched schematic pin label:

Labeled Schematic Pin | Matched Layout Pin | Matched Layout Net
--------------------------+------------------------+-----------------------
GND! |                              ** missing pin ** |                 19
vdd! |                                ** missing pin ** |                 43

First, I don't have GND! in schematic, only gnd!.

Second, the layout nets gnd! (net 19) and vdd! (net 43) appear to be correctly connected upon visual inspection, so I'm not sure why the LVS is failing to match them.

BTW I do have a pin on M1, M2, M3, M4, still same error.

Here is an image of LVS output.

https://postimg.cc/yDTBMFJM

Thank you.

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