Modgen: How to add dummy FETs sharing diffusion without issues of marker layers?

Hello,

I am trying to use Modgen to create dummies and I am having issues understanding what I am doing wrong. Thus the sloppy title, for which I apologize.

I'll try to explain my methodology and what is my issue chronologically.

Also, please note I'm not an expert at all and maybe my understanding is wrong or my approach not best practice, do not hesitate to tell me if it is so.

I am using ICADVM 18.1

First of all, please note the following ; the PDK I am using uses the following marker layer : 

The FETs Pcells I am using have dummy & stop polys, and AUXPC automatically generated when RX ends (see picture below).

Note: In all my pictures, on the left both PC and AUXPC will be visible, on the right only AUXPC.

Now, using Modgen, I am creating dummies which I will short to gnd!

I do not want to simply use the Abut All function to horizontally space the FETs as I do not want the dummies' drains which are tied to ground (around the main gate) to overlap with my active FETs' drains.

But I still want them to share the same diffusion.

Effectively, I'd like to do the following (see picture below). Here, there is only one active FET and no dummies above and below.

See how the AUXPC only ends, as it should, at RX end.

Using Abut merges the dummies one poly lines further inside, which I would like to avoid as described above.

Thus, in Modgen I am using Member Alignment and Spacing to achieve what I did manually above. Note that here, vertical alignment is bigger just to make the picture clearer.

However, this way the Pcell do not detect that the RX does not end in between the different FETs, and thus I it is present in the middle of RX (here there are two active FETs in between the dummies):

And this is an issue... It breaks DRC & LVS.

The Pcells do not have a switch or property to change or override this AUXPC generation.

Thus I am unsure of the following:

• Is there a way in Layout to override an instance's layers (as in, is it possible to tell Virtuoso to exclude a given layer of the Pcell's output? this way I could then add the AUXPC manually)
• Am I not generating these dummies properly, is it not how it is supposed to be done at all? I found very few detailed practical information

Currently, my solution is simply to either manage them manually, or to space the dummies more but then they'll not share diffusion with the active FETs...

Thank you very much in advance!

Regards.