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Virtuoso PEX "Nothing in Layout" Issue

AR202509099018

Dear All,

Hi, I ran into the above error when performing PEX in Cadence Virtuoso for a standard cell. The Cell was clean in both DRC and LVS stages, but it runs into this error at PEX stage. Due to the length of the PEX log, I have just attached it as a separate file to this post. I'd be grateful, if someone could shed a light on to this matter to get PEX run successful.

https://sharetext.io/4f57e923

Thanks in advance.

Anuradha

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  • Andrew Beckett

    Anuradha,

    You're using Calibre in this case. Calibre is not a Cadence tool - it's from Siemens EDA - both the tool and the interface to it are from them, even though you are running in Virtuoso. You should ask this question in a Siemens EDA forum or to their customer support.

    Regards,

    Andrew

  • AR202509099018
    in reply to Andrew Beckett

    Thanks for your clarification. May be you can help me with this one simple thing. In my layout, the transistors are not available as PCELLs. However, their geometries are drawn in full custom mode. So the transistors exist according to the specified schematic information, therefore the circuit is DRC/LVS clean! This should be the case, right? 

  • Andrew Beckett
    in reply to AR202509099018

    There's no requirement for LVS for the transistors to be PCells. Provided the geometries are drawn correctly and the device can be recognized according to the rule deck, it should be fine.

    Andrew

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  • Andrew Beckett
    in reply to AR202509099018

    There's no requirement for LVS for the transistors to be PCells. Provided the geometries are drawn correctly and the device can be recognized according to the rule deck, it should be fine.

    Andrew

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