Stats

  • Replies 0
  • Subscribers 125
  • Views 27
  • Members are here 0

How do you draw a parametrized layout of an inverter ?

MC20250412421

Hi everyone !

I have a simple schematic cell of a CMOS inverter which has pPar("W") parameter for my transistor widths.
I am now trying to do the layout of this inverter and I want to make the layout follow the pPar("W") parameter too.
I am using my pdk's transistors which are themselves pcells and scale correctly with the W parameter.

The issue is that I don't find the documentation on how to make this parametrized layout or even how to start doing that layout.

Can anyone point me to the right resources or tell me how to start doing such a layout ?
I would really appreciate that.

Thanks in advance and have a great day !

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.