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Replace symbol pin names without changing the pin placement and symbol boundary

SimhanAnalog

Say I have a symbol with a few pins 

o_h<2:0>

o_m

o_a<1:0>
o_b<3:0>

i_c<1:0>

i_d<2:0>

i_f<5:0>

i_g

i_s<3:0>

Say I want to rename the pins as follows retaining the same bit widths

o_b -> o_y

o_a -> o_x

i_d -> i_z

I want to ensure that the symbol dimensions and pin placements remain same so that the schematic where this symbol is instantiated and connections are made is intact.

I will like to provide this pin changes in a text file like below

o_b, o_y

o_a, o_x

i_d, i_z

Is there a simple way to do this? Or does cadence already has some api that can do this?

Thanks

  • Andrew Beckett
    in reply to SimhanAnalog

    You'd need to write some SKILL code to do this. I don't know of anything that does this, although maybe this will help as a starting point: SKILL: How to change a given pin name in a symbol / schematic ? (I haven't looked to see how good that code is - it's quite old).

    Andrew

  • SimhanAnalog
    in reply to Andrew Beckett

    Thanks. I was able to get something working using

    loop across all terminals in symbol

    if terminal needs to be replaced(part of the old port column in csv) do the following  

    term~>name = new_name

    But I get the following warning for which I just need to open the symbol and click check and save and it goes away. This warning I get only for the last port on my list.

    Warning: Port "last_new_port<4:0>" in "cell_name symbol" not specified in the portOrder property.

    Warning: Port "last_old_port<4:0>" in the portOrder property not found in "cell_name  symbol".
    Is there a skill way to do it.


    I tried 
    schVIC(cv)
    dbSave(cv)

    But it doesn't help(maybe these commands are old). It goes away if I manually open symbol view and click check and save.

  • SimhanAnalog
    in reply to SimhanAnalog

    I got it working by adding 

    hiEnqueueCmd("hiDBoxUser(schReplaceOrModifyDialog nil 2)")
    schViewToView(lib_name_d module_name lib_name_d module_name "systemVerilog" "symbol" "_vmsSVVmsToPinList" "schPinListToSymbolGen")
    and again doing
    schVIC(cv)
    dbSave(cv)

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