Stats

  • Replies 1
  • Subscribers 130
  • Views 600
  • Members are here 0

Strategy for Accelerating Full-Chip AMS Simulation with Multi-Rate Clocks (1kHz / 100MHz)

HY202510149941

Hello Support Team,

I am writing to request guidance on optimizing a very slow AMS simulation for a full System-on-Chip (SoC) design.

Our Environment:

  • Virtuoso Version: IC6.1.8

  • Spectre Version: 21.1

  • Simulation Type: AMS Designer (transient analysis)

  • Scope: Full-chip level, including all PADs.

  • Input Files:

    • Digital Blocks: We are using Verilog files for the design and SDF files for timing annotation.

    • Analog Blocks: We are using DSPF files (from PEX) for parasitic extraction.

The Problem:

We need to run a transient simulation for a total time of 80ms.

The primary challenge is that our chip uses highly divergent clock rates:

  1. Slow Clock: 1kHz

  2. Fast Clock: 100MHz

We anticipate this combination will result in a prohibitively long simulation time. We have not yet been able to run the full 80ms simulation because we expect it to be unfeasible, even if we switch the solver to Spectre VX (Spectre X)

Our Question:

What are the recommended solutions or best practices for accelerating an AMS simulation with such a wide discrepancy in clock frequencies?

Thank you for your help.

  • Alonso Schmidt

    Hi,

    This looks very much like a good application of our Spectre FX FastSPICE simulator, due to three things:

    • Full SoC simulation
    • Accuracy requirements are not high, as you trying Spectre X VX mode suggests.
    • Spectre FX has technology specific to partitioning and multi-rate simulation.

    If you have a license for it, I suggest updating your tool versions to the latest you can (Spectre, Xcelium) and trying it out.

    Without FastSPICE, what you can normally do to speed up full-chip simulations is to employ behavioral models for analog blocks, especially wreal and System Verilog Real Number Modelling (SVRNM) to avoid using the time-step based analog solver. You could limit DSPF only to parts where it is critical to model post-layout effects.

    Beyond that, I would suggest you file a case at ask.cadence.com to discuss your simulation needs in more depth.

     

    Best regards,

    Alonso

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.