Strategy for Accelerating Full-Chip AMS Simulation with Multi-Rate Clocks (1kHz / 100MHz)

Hello Support Team,

I am writing to request guidance on optimizing a very slow AMS simulation for a full System-on-Chip (SoC) design.

Our Environment:

• Virtuoso Version: IC6.1.8

• Spectre Version: 21.1

• Simulation Type: AMS Designer (transient analysis)

• Scope: Full-chip level, including all PADs.

• Input Files:

  • Digital Blocks: We are using Verilog files for the design and SDF files for timing annotation.

  • Analog Blocks: We are using DSPF files (from PEX) for parasitic extraction.

The Problem:

We need to run a transient simulation for a total time of 80ms.

The primary challenge is that our chip uses highly divergent clock rates:

1. Slow Clock: 1kHz

2. Fast Clock: 100MHz

We anticipate this combination will result in a prohibitively long simulation time. We have not yet been able to run the full 80ms simulation because we expect it to be unfeasible, even if we switch the solver to Spectre VX (Spectre X)

Our Question:

What are the recommended solutions or best practices for accelerating an AMS simulation with such a wide discrepancy in clock frequencies?

Thank you for your help.