Transfer design variable from schematic / layout to av_extracted view

Hi Cadence Community,

I am using the following software: Virtuoso Studio version IC23.1-64b.ISR7.27.

I have written a Verilog-A model, created the symbol and a schematic (including the symbol). This model has a float variable. In the property dialog of the symbol, I could select this Verilog-A variable and assign a design variable name to it (my_var). Later, I assigned different values to my_var in a maestro file to check how my circuit behaves with different values. So far everything works as expected. Next, I have created a layout including this model and I can see the Verilog-A variable still includes my_var. I configured all necessary tools to generate the av_extracted view with Pegasus-Quantus. Afterwards, I noticed that my_var was replaced by the default CDF value of the Verilog-A variable in the av_extracted view. 

Does someone know how to ensure that my_var is transferred from the schematic / layout into the av_extracted view and not the default CDF value?

Felix