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Question on integrated noise in PNOISE (sampled) Noise summary

Yuto Lau

Hi everyone,

I have a circuit including two stage, 1st stage is a CML buffer, 2nd stage is differential to singled ended amplifier. In CML stage, differential pair is driving resistor load.

Input clock is the same frequency square wave. In 1st t test (test1), differential input clock swing is 200mV, in 2nd test (test2) differential input clock swing is 100mV, but the rise time, fall time in two test are the same. So the slope in test2 is half of that in test1.

I ran sampled PNOISE on this circuit with input clock mentioned above, and then check the noise summary report for input, and each stage output respectively. And in the noise summary, I set integrated output noise from 100kHz to half of clock frequency (fundamental freq.). And integrated output noise in unit V^2.

I compared output noise reported in noise summary, Jee against these two tests as below,

1) At input, integrated noise is the same in two tests.  Jee for test1 is nearly half of test2. It makes sense to me. The clock slope makes the difference in Jee.

2) At 1st stage output, integrated noise is also the same in two tests. Difference in Jee aligns to difference in clock slope. 

3) At 2nd stage output, integrated noise in test2 is almost 1.5x of test1 (each component shows 1.5x noise in test2 compared to test1.). And clock slope in test2 is ~ 0.56x of that in test1. Jee in test2 is ~2x of Jee in test1. 

My question is

What factor probably have impact to output noise in sampled PNOISE?

I have thought that integrated output noise in sampled PNOISE should be the same regardless of clock swing or slope. clock slope only impacts jitter or edge phase noise. Because output noise spectrum is the same and then it is folded back by ideal sampling. This thought align to 1st stage output result.

But integrated output noise at 2nd stage in test2 is different from test1. It tells my understand is wrong. What factor else leads to that difference?

Thanks and regards,

Yutao

Parents
  • Frank Wiedmann

    You can list the noise contributors by printing the noise summary, see for example https://support.cadence.com/apex/techpubDocViewerPage?path=Explorer/ExplorerIC25.1/chap9.html#pgfId-1048767 . This should allow you to find out where the difference comes from.

  • Yuto Lau
    in reply to Frank Wiedmann

    Hi Frank,

    Thanks for your reply.

    Yes, I did print noise summary at 2nd stage output to compare noise contributors against test 1 and test 2, and find that each contributor in test2 has ~1.5x more noise than test1 counterpart.

    I have thought that it calculate output noise spectrum based on operating point at the threshold we set in sampled pnoise, and then fold back noise higher than half of fundamental frequency back due to the ideal sampling. In this case, then output noise should be the same regardless of input clock slope nor swing. However, sim result does not agree with my thought.

    So what fact to output noise did I miss?

    Thanks and regards,

    Yutao

Reply
  • Yuto Lau
    in reply to Frank Wiedmann

    Hi Frank,

    Thanks for your reply.

    Yes, I did print noise summary at 2nd stage output to compare noise contributors against test 1 and test 2, and find that each contributor in test2 has ~1.5x more noise than test1 counterpart.

    I have thought that it calculate output noise spectrum based on operating point at the threshold we set in sampled pnoise, and then fold back noise higher than half of fundamental frequency back due to the ideal sampling. In this case, then output noise should be the same regardless of input clock slope nor swing. However, sim result does not agree with my thought.

    So what fact to output noise did I miss?

    Thanks and regards,

    Yutao

Children
  • Frank Wiedmann
    in reply to Yuto Lau

    A sampled pnoise analysis does not just consider the operating point at the threshold. Rather, it takes into account the behavior of the circuit during the entire period and calculates its effect on the noise at the time of the threshold crossing. So in test2, your circuit probably spends more time in a state where it accumulates noise, for example on a (parasitic) capacitance.

    For some background information, you might want to take a look at https://designers-guide.org/analysis/sc-filters.pdf . When that article was written, the sampled analysis types did not exist yet. All that was available for this purpose was pnoise with noisetype=timedomain.

  • Yuto Lau
    in reply to Frank Wiedmann

    Hi Frank,

    Thanks for your reply.

    Your explanation makes more sense to me. I should NOT consider steady-state operating point as a group of dc operating point with in a clock period.

     Regards,

    Yutao 

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