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AMS Unified Netlisting Creates Incomplete Netlist

msharma

I am using the ams simulator for a test bench schematic with mixed SystemVerilog and, schematic and extracted views. The netlist.vams file has only two lines:
`include "disciplines.vams"
`include "userDisciplines.vams"

Rest of the lines are just comments, including comments for HDL files.

Therefore, "Netlist & Run" succeed at Netlist step, and fails in the elaboration step.

I believe that the AMS Unified Netlister finishes before the Spectre net lists of the analog blocks are created. This could be because the digital blocks Netlist faster compared to the analog blocks, especially the extracted views.
Is there a way to get the AMS correct netlist which includes the analog blocks as well?

PS:
Also, I saw this line at the beginning of the netlisting:
"Reusing AHDL Data dir"
Is it possible to not reuse the AHDL Data dir, and possibly it helps in the above problem?

  • msharma

    I am using the ams simulator for a test bench schematic with a mixture of  SystemVerilog, schematic and extracted views. After the netlisting step, the netlist.vams file has only two lines:
    `include "disciplines.vams"
    `include "userDisciplines.vams"

    Rest of the lines are just comments, including comments for HDL files. i.e. the netlist is basically empty. The cells with schematic or extracted views are not referenced.

    The, "Netlist & Run" succeed at the netlisting step, and fails in the elaboration step.

    I believe that the AMS Unified Netlister finishes prematurely before the creation of the Spectre netlists of the analog blocks. This could be because the digital blocks netlist faster compared to the analog blocks, especially the extracted views.
    Is there a way to get the AMS to generate a correct netlist which includes the analog blocks as well?

    PS:
    Also, I saw this line at the beginning of the netlisting:
    "Reusing AHDL Data dir"
    Is it possible to not reuse the AHDL Data dir, and possibly it helps in the above problem?

  • Andrew Beckett
    in reply to msharma

    Asking the same question twice won't get it answered any sooner (so I merged your two separate questions into one thread to avoid confusion).

    The Reusing AHDL Data Dir won't make a different here (that's related to Verilog A compilation). 

    It's hard to know what's not working - I suggest you contact customer support (submit a case after logging in using the Case menu) so that an Application Engineer can take a look at the data in more detail than is feasible in a forum post.

    Andrew

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