clock buffer output RJ and edge phase noise result "diverges"

Hi everyone,

I ran sampled PNOISE sim on a CML clock buffer , with 100MHz and 156.25MHz input clock respectively.

 "fullspectrum" was selected in "Sidebands".

Edge phase noise was plot and RJ was measured. RJ integration range is from 100kHz to 1MHz, as a 1MHz BW PLL will be after the clock buffer.

1) Their transient waveform looks similar. Output swing with 100MHz is 729mV, rising edge rate is 15.61V/ns; Output swing with 156.25MHz is 727mV, edge ratei is 15.85V/ns. 

2) Edge phase noise with 100MHz input clock is ~2.7dB lower than that with 156MHz. I agree with the trend, because 100MHz case has a lower carrier frequency.

3) RJ integrated from 100K to 1MHz shows opposite result. RJ with 100MHz is ~1.2x larger than 156.25MHz counterpart. Output noise spectrum with 100MHz is also ~1.2x larger than 156.25MHz counterpart.

4) Even though I add another RJ measurement point at a noisy resistor in front of the buffer, I still see 100MHz case has a higher RJ.

Why does 100MHz case has a higher output noise spectrum?  Is it correct to set "fullspectrum"?

In "Designers' Guide Simulating Switched-cap filter with SpectreRF ", it is mentioned  that noise power density at the hold phase after aliasing is inverse proportional to clock frequency. Because overall noise power is kT/C is split into more rectangle with lower clock frequency and then is folded back.  Is it the reason?

How should I understand the discrepancy in edge phase noise and RJ? When I estimate this buffer's contribution to 1MHz PLL output jitter, which result should I use?

Thanks and regards,

Yutao