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Parasitic capacitance

SamanMKD

Hello everyone,

In my mm-wave design, the MOM capacitor shows a high value of parasitic capacitance (total coupling parasitic capacitance = 24.57 fF) as it can be seen in figure.The MOM-cap is a P-cell. Any suggestions to overcome and suppress this parasitic capacitance?



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  • Andrew Beckett

    You didn't say which extraction tool you're using for parasitic extraction or which technology this is, but usually such cells would have blocking setup to prevent extraction of parasitics within a characterised layout like this.

  • SamanMKD
    in reply to Andrew Beckett

    Hi Andrew, Thank you for your reply. I used Calibre PEX. and It is CMOS 28nm node.

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  • SamanMKD
    in reply to Andrew Beckett

    Hi Andrew, Thank you for your reply. I used Calibre PEX. and It is CMOS 28nm node.

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  • Andrew Beckett
    in reply to SamanMKD

    "CMOS 28nm node" is not very specific - that could be any foundry!

    Anyway, since you're using Calibre (which is not a Cadence tool, but sold by Siemens EDA), you would be better off asking this on a Siemens EDA forum or to their customer support. You might find people with the experience on Cadence forums who can answer this, but the odds are higher if you ask on a forum related to the tool you're using...

    Andrew

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