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  3. Syntax errors when utilising idt() in bsource

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Syntax errors when utilising idt() in bsource

GT20260122746
GT20260122746 1 hour ago

Hello, 

I am trying to model a behavioural current source in the spectre netlist, and I am running into some issues, as I cannot find much documentation on the problem.

From my understanding, I should be able to use idt() functions in these sources and (I think) the syntax is:

idt(x a assert)

Where a is the intiial condition and assert is the conditional expression to assert this condition.

I model my source like:

parameters var1 = 100

dummyR (N1 N2) resistor r = 10

TestSource (N2 0) bsource i = idt(v(N1) > 1 && v(N1) < var1 ? (2*i("dummyR:1")) : 0) 0 v(N1) < 1)

Which, if I understand correctly will integrate the expression (2*i("dummyR:1")) if the two conditions v(N1) > 1 && v(N1) < var1 are true, and will assert to 0 when v(N1) < 1.

Worth noting, this is connected to some sources at N1. I am porting this from an LTSpice model, which works as expected.

The above gives me errors: 

Error: Illegal parameter name `0' specified, please do not use `number name' as the parameter name.

Error: Cannot run the simulation because syntax error `Unexpected operator "<". Expected end of file or end of line' was encountered at line 85, column 104. Correct the syntax error and rerun the simulation.

Have I misunderstoof the syntax? Or have I misunderstood the implementaion of idt() in the spectre enviroment? I saw in "Virtuoso Spectre Circuit Simulator User Guide" page 87, that bsource i should take a generic_expr which:

A simple expression that may contain idt () or ddt() as well.

Any help appreciated.

Thanks.

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  • GT20260122746
    GT20260122746 1 hour ago

    As an update, I found the correct syntax required:

    idt(x, a, assert)

    so:

    TestSource (N2 0) bsource i = idt(v(N1) > 1 && v(N1) < var1 ? (2*i("dummyR:1")) : 0, 0, v(N1) < 1)

    And it now doesn't throw the errors, but when I got to simulate I get:

     ERROR (SFE-2326): "..." 83: The 3 argument of function `idt' does not support behavioral expressions.

    Which i'm guessing is meaning it doesn't like the < in the assert? But then I think I am not understanding how to translate this from LTSpice, as this mechanism works there. 

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  • Andrew Beckett
    Andrew Beckett 3 minutes ago in reply to GT20260122746

    You're probably better off using a VerilogA model if you need something more complicated.

    Otherwise, contact customer support so that we can look at it in more detail.

    Andrew

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