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Phase Noise Simulation

TH202510293247

Hi,

I have very basic doubt regarding phase noise and edge jitter simulation.

I have a simple circuit as shown below:
10 MHz clock (square wave) connected to a buffer driving a capacitive load.




Now I run PSS + PNOISE simulation (setup shown below)


I have obtained the edge phase noise spectrum via sampled jitter. Settings shown below:

I was expecting the same phase noise plot. However, that obtained from the sampled method is ~3dB worse compared to the phase noise from time average....
And consequently the edge jitter numbers in the two cases is off by a factor of sqrt(2). Can please help me understand which one is correct and what I am missing over here?

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