Simulating SAR ADC CDAC (floating nodes)

Hello! I am trying to design a differential 4-bit SAR ADC in Cadence. I am currently testing the capacitive DAC alone to ensure I get the correct voltage values as I manually switch ON and OFF the switches on the capacitive array.

From my understanding, during the conversion cycle the top plates of the capacitors must "float", but when performing the simulations I don't see this behaviour and sometimes I get convergence issues (which I believe is because I eliminate any DC path to ground when disconnecting the input voltage from the capacitor top plates). I added a high resistance path to ground to see if that would help but it didn't.

Is there a particular way I must perform these types of simulations that involve floating nodes?

Thank you in advance for your help! Best regards.