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Verilog Parsing Fails

OOMR

Hi,

I created a verilog view from my symbol in Vituoso and it fails HDL compilation.  This is just a stub created by the tool and it fails right out of the box.

*WARNING* (TE-4309): Extract failed for cellview 'rpackard_lib xnepwrsuphkiehv_aip functional'
Successfully save the HDL compilation setting.
(TE-7051): Saved changes to /nfs/site/disks/xne_iptfmdev_005/rpackard/work_1278p3_26ww18p4_source_xneclklvt/opuslib/rpackard_lib/xnepwrsuphkiehv_aip/functional/verilog.v
(TE-4223): Extracting cellview 'rpackard_lib xnepwrsuphkiehv_aip functional' ...
ERROR (SHDB-11): Failed to parse the verilog module for design unit (rpackard_lib xnepwrsuphkiehv_aip functional). Either there are compilation
errors or cellview is not writable or verilog module does not exist in the file.
ERROR (TI-7001): Cannot load the connectivity information for cellview 'rpackard_lib/xnepwrsuphkiehv_aip/functional' in text file
'/nfs/site/disks/xne_iptfmdev_005/rpackard/work_1278p3_26ww18p4_source_xneclklvt/opuslib/rpackard_lib/xnepwrsuphkiehv_aip/functional/verilog.v'.
Verilog *E,PARSEERR: Either there are parsing errors or cell xnepwrsuphkiehv_aip
is not found in /nfs/site/disks/xne_iptfmdev_005/rpackard/work_1278p3_26ww18p4_source_xneclklvt/opuslib/rpackard_lib/xnepwrsuphkiehv_aip/functional/verilog.v

Cadence version 23.1.ISR10

I have the HDL package enabled, too.

Thaks


Rich

Parents
  • Andrew Beckett

    Rich,

    Is the module name in the Verilog text different from the cell name for the cellView? If it is, that produces this error.

    Andrew

Reply
  • Andrew Beckett

    Rich,

    Is the module name in the Verilog text different from the cell name for the cellView? If it is, that produces this error.

    Andrew

Children
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