Recommended methodology for PSRR characterization of a clocked regenerative comparator

Hi all,

I am trying to characterize the PSRR of a clocked regenerative comparator (StrongARM-type latch), and I am struggling not only with the simulator setup itself but also with the definition of PSRR for a latched comparator.

For switched-cap amplifiers and other periodically time-varying but small-signal linear circuits, the usual SpectreRF flow (PSS followed by PAC/PXF) makes sense because the circuit can be linearized around its periodic operating point and the output is a continuous analog quantity.

A regenerative comparator seems fundamentally different. Around the decision point, the small-signal gain becomes extremely large, and the final output is binary (either 0 or VDD). A very small perturbation in the input or supply can completely change the final decision. Because of this, I am having difficulty understanding what an "output-referred PSRR" would even mean.

My concern is that a PSS+PXF flow may not provide a meaningful PSRR metric in this case, unless there is a specific methodology or interpretation that I am missing.

Intuitively, it seems that supply noise should manifest itself as one of the following:

1. An input-referred offset shift (equivalent input error due to supply variation),

2. A change in decision time,

3. A change in metastability probability or decision error rate.

So my questions are:

• Can PSS/PAC/PXF be meaningfully applied to this type of circuit, and if so, how should the results be interpreted?

• Is there a recommended Cadence/SpectreRF methodology for characterizing supply sensitivity of a clocked comparator?

I would appreciate any guidance or references on how others typically characterize PSRR or supply sensitivity for dynamic comparators.

Thanks in advance.

Can