Liberate for characterizing emerging transistor technology

Hi there,

I'm developing a PDK/library for an emerging transistor technology. I've developed and validated a level-61 spice model for the transistors (non-Si-based) and the model can run in Spectre. The next step is to build standard cells for logic gates, characterize them, and generate .lib timing/power models for use in digital design and system-level evaluation.

I'm new to Liberate and was wondering if it is the right tool for this task. In particular:

1. Can Liberate characterize custom transistor-level cells using Spectre with a Level-61 device model? My understanding is Liberate should not depend on the internal transistor technology of the cell. As long as the Level-61 model is supported by Spectre, and Liberate can invoke Spectre on the transistor-level netlists, Liberate should be able to characterize the cells. Is that correct?
2. Can I start with schematic-level/pre-layout netlists, and later move to PEX-extracted netlists?

Any guidance or pointers would be greatly appreciated. Many thanks!

All the best,
Kevin