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  3. Automatic Chaining in Layout GXL

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Automatic Chaining in Layout GXL

Dhruv N Patel
Dhruv N Patel 1 day ago


Hi everyone,

I'm working in Cadence Virtuoso Layout GXL 6.1.8 with two NMOS transistors, M0 and M1, each having a multiplier of 2 (m = 2) and a single finger (nf = 1).

The schematic shown is just a simplified example to illustrate the issue, not an actual circuit implementation.

For the purpose of interdigitation, I'm trying to place one physical transistor from M0 next to one from M1 and overlap their adjacent source diffusion regions to create a shared source diffusion, since both sources are connected to the same net (GND).

I initially tried using the Automatic Chaining feature, but it did not arrange or abut the transistors as intended, regardless of whether "Update Connectivity When Design Is Modified" was enabled or disabled. Therefore, I decided to try positioning and overlapping the transistors manually.

However, I've noticed the following behavior:

  • Figure 1: When "Update Connectivity When Design Is Modified" is enabled (highlighted in the screenshot), Virtuoso does not allow me to overlap the two source diffusion regions, even though both are connected to GND.
  • Figure 2: When this option is disabled, I can move the two transistors closer together and overlap their source diffusion regions.

I'm trying to understand:

  1. Why does enabling this option prevent the overlap, even though both source terminals are connected to the same net?
  2. Is this behavior related to the PDK/PCell abutment rules, or is it a general restriction of connectivity-driven layout in Virtuoso?
  3. Is there a recommended way to achieve shared source diffusion between transistors belonging to different schematic devices during interdigitation while keeping connectivity updating enabled?
  4. Could manually overlapping the transistors with connectivity updating disabled introduce connectivity or layout issues, even if both source terminals are on the same net?
  5. Is there a particular setting or requirement for Automatic Chaining to recognize and arrange these transistors with shared source diffusion?

I'd appreciate any clarification on why this happens and how Virtuoso handles diffusion sharing in this situation.

Thanks!

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