Custom IC Design

Latest Posts

Discussion

Gain margin and phase margin expressions from nyquist plots

Category: Custom IC Design

By unSkilled
•
updated over 2 years ago by ShawnLogan

6 replies • 10979 views
Discussion

Plot S parameters as a function of gm/id -RF characterization of MOSFET

Category: Custom IC Design

By LAKSHMINS
•
started over 2 years ago

0 replies • 594 views
Discussion

Best strategy for adding dummies for CC placement

Category: Custom IC Design

By supriyo1985
•
updated over 2 years ago by supriyo1985

3 replies • 7418 views
Discussion

Defining Verilog-A vector in the maestro view

Category: Custom IC Design

By TomVilla
•
updated over 2 years ago by Andrew Beckett

3 replies • 8118 views
Discussion

How to Access Reliability Report in Reliability RAK

Category: Custom IC Design

By AllesNormell
•
updated over 2 years ago by AllesNormell

11 replies • 7995 views
Discussion

For rotation of any polygon in layout which is made by SKILL IDE

Category: Custom IC Design

By Upendra Ch
•
updated over 2 years ago by Andrew Beckett

3 replies • 6136 views
Discussion

Cadence Simulation

Category: Custom IC Design

By Upendra Ch
•
updated over 2 years ago by Upendra Ch

3 replies • 5724 views
Discussion

Input through .VEC file

Category: Custom IC Design

By PrateekSharma
•
updated over 2 years ago by Andrew Beckett

2 replies • 5472 views
Discussion

why diffusion sharing not possible

Category: Custom IC Design

By supriyo1985
•
updated over 2 years ago by supriyo1985

2 replies • 5687 views
Discussion

Display dimming bindkey stops working after ascending or descending hierarchy

Category: Custom IC Design

By akhmathew
•
updated over 2 years ago by Andrew Beckett

2 replies • 6398 views
Discussion

i want to do that kind of simulation with cadence, but i don't know how to do it ?

Category: Custom IC Design

By Hagar Hendy
•
updated over 2 years ago by ShawnLogan

7 replies • 2659 views
Discussion

Could not find netlist procedure: _spectreCap instance

Category: Custom IC Design

By CJYEHRAYRAY
•
updated over 2 years ago by Andrew Beckett

3 replies • 2452 views
Discussion

QRC's av_extracted view is not showing any parasitic resistotrs and capacitors and metal layers

Category: Custom IC Design

By LAKSHMINS
•
updated over 2 years ago by Andrew Beckett

3 replies • 1705 views
Discussion

slow vias arrays

Category: Custom IC Design

By ascott
•
updated over 2 years ago by ascott

4 replies • 5600 views
Discussion

IC618 cannot find files to start

Category: Custom IC Design

By jeffreylao
•
updated over 2 years ago by jeffreylao

7 replies • 12010 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.