Custom IC Design

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Discussion

Location of VXL user guide please

Category: Custom IC Design

By kenc184

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updated over 3 years ago by kenc184

2 replies • 10902 views
Discussion

is there a way to change the design for multiple tests simultaneously?

Category: Custom IC Design

By delgsy

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updated over 3 years ago by delgsy

2 replies • 9477 views
Discussion

License issue while plotting outputs

Category: Custom IC Design

By Hao Guo

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updated over 3 years ago by Hao Guo

5 replies • 10496 views
Discussion

tags in VXL layout

Category: Custom IC Design

By kenc184

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updated over 3 years ago by kenc184

2 replies • 6457 views
Discussion

Simulation of encrypted spectre netlist

Category: Custom IC Design

By analogdesign

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updated over 3 years ago by Andrew Beckett

1 replies • 10313 views
Discussion

Accessing waveform generated by a maestro expression in Matlab using adeInfo

Category: Custom IC Design

By michael10

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updated over 3 years ago by Andrew Beckett

1 replies • 9374 views
Discussion

Problem with systemVerilog netlister in IC618 which stops with cryptical message on a digital schematics in Virtuoso

Category: Custom IC Design

By Emulator

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updated over 3 years ago by Emulator

2 replies • 10881 views
Discussion

How to clear the DRC warning highlights from my layout

Category: Custom IC Design

By Senan

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updated over 3 years ago by Senan

2 replies • 11747 views
Discussion

Import Data to Cadence

Category: Custom IC Design

By Julinshah

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updated over 3 years ago by Andrew Beckett

7 replies • 22221 views
Discussion

Parameterizing PSP model card parameters, for ADE parametric Analysis

Category: Custom IC Design

By araol

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updated over 3 years ago by Andrew Beckett

3 replies • 9971 views
Discussion

ADE Datasheet Generation Problems

Category: Custom IC Design

By SteveDobbs

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started over 3 years ago

0 replies • 8411 views
Discussion

Boolean operations in Virtuoso Layout Editor

Category: Custom IC Design

By shlomo34

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updated over 3 years ago by shlomo34

2 replies • 12703 views
Discussion

Checking for LUP and HVESD on cell-level DRC run

Category: Custom IC Design

By Jin W Kwak

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updated over 3 years ago by Andrew Beckett

3 replies • 14338 views
Discussion

multicore AMSD run

Category: Custom IC Design

By sv srini

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started over 3 years ago

0 replies • 8449 views
Discussion

Problem with terminals definition in a spice component

Category: Custom IC Design

By nasetrop

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updated over 3 years ago by nasetrop

4 replies • 10673 views

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