Custom IC Design

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Discussion

How to check the load capacitance of a node in cadence virtuoso?

Category: Custom IC Design

By zuiying

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updated over 3 years ago by Andrew Beckett

6 replies • 24098 views
Discussion

Net Highlighting without appearing staggered lines

Category: Custom IC Design

By billgzhsu

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updated over 3 years ago by billgzhsu

6 replies • 11597 views
Discussion

Copy single test between ADE Assembler maestro files?

Category: Custom IC Design

By TempViator

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updated over 3 years ago by Andrew Beckett

1 replies • 10588 views
Discussion

parasitic exclusion not working in PAD

Category: Custom IC Design

By Pirate King

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updated over 3 years ago by Pirate King

1 replies • 8592 views
Discussion

Wire Assistant in layout loosing connectivity

Category: Custom IC Design

By Senan

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updated over 3 years ago by Senan

4 replies • 10333 views
Discussion

LVS Port Mismatch Errors with CDL Netlist

Category: Custom IC Design

By amrao

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updated over 3 years ago by Andrew Beckett

3 replies • 11789 views
Discussion

How to use a CSV file in Cadence?

Category: Custom IC Design

By Sachin Mishra

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updated over 3 years ago by Sachin Mishra

6 replies • 20400 views
Discussion

Can I generate layout from source but not from the same hierarchy level?

Category: Custom IC Design

By delgsy

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updated over 3 years ago by delgsy

8 replies • 11440 views
Discussion

Passing LVS without making the well tap in the current hierarchy

Category: Custom IC Design

By delgsy

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started over 3 years ago

0 replies • 8467 views
Discussion

Inclusion of Spectre analysis statements via include file in ADE: How to control it?

Category: Custom IC Design

By StephanWeber

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updated over 3 years ago by Andrew Beckett

3 replies • 10334 views
Discussion

How can I use a paramset to define a dc simulation for certain parameter combinations?

Category: Custom IC Design

By StephanWeber

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updated over 3 years ago by Marc Heise

1 replies • 9051 views
Discussion

stability analysis RC coupled Vs RC decoupled

Category: Custom IC Design

By Pirate King

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updated over 3 years ago by Pirate King

3 replies • 9664 views
Discussion

probe a structure for all layout layers used in its build?

Category: Custom IC Design

By kenc184

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updated over 3 years ago by kenc184

5 replies • 9368 views
Discussion

Layout XL : Connectivity - Update Function

Category: Custom IC Design

By amssshubham

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updated over 3 years ago by Andrew Beckett

4 replies • 6570 views
Discussion

Cadence understand Poly resistor as a poly contact problem

Category: Custom IC Design

By Senan

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updated over 3 years ago by Senan

4 replies • 13266 views

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