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Custom IC Design

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  • Discussion

    VerilogA models in Cadence

    Category: Custom IC Design

    By Sali Sali

    •

    updated over 11 years ago by Sali

    12 replies • 21077 views
  • Discussion

    LVS does not accept proper termOrder

    Category: Custom IC Design

    By Kabal Kabal

    •

    updated over 11 years ago by Kabal

    9 replies • 19012 views
  • Discussion

    Adding Layout block from Encounter to custom design

    Category: Custom IC Design

    By Kabal Kabal

    •

    updated over 11 years ago by Andrew Beckett

    6 replies • 15980 views
  • Discussion

    How-to edit CGSO and CGDO parameters and resimulate

    Category: Custom IC Design

    By cozdag cozdag

    •

    updated over 11 years ago by Andrew Beckett

    1 replies • 14548 views
  • Discussion

    Parasitic extraction of standalone metal traces (IC6.1.5)

    Category: Custom IC Design

    By Wes8 Wes8

    •

    updated over 11 years ago by Andrew Beckett

    1 replies • 14471 views
  • Discussion

    How to add noise in v source?

    Category: Custom IC Design

    By madhusudha madhusudha

    •

    updated over 11 years ago by Andrew Beckett

    3 replies • 27947 views
  • Discussion

    Transient Noise Analysis | Noise File

    Category: Custom IC Design

    By pitter pitter

    •

    updated over 11 years ago by Andrew Beckett

    3 replies • 17657 views
  • Discussion

    Hierarchy Editor - Setting schematic view recursively within a tree

    Category: Custom IC Design

    By cdonovan cdonovan

    •

    updated over 11 years ago by cdonovan

    2 replies • 2265 views
  • Discussion

    DRC error in resistor layout

    Category: Custom IC Design

    By whitefan whitefan

    •

    updated over 11 years ago by whitefan

    1 replies • 14412 views
  • Discussion

    Getting back source layout from gds

    Category: Custom IC Design

    By ImonMondal ImonMondal

    •

    updated over 11 years ago by ImonMondal

    2 replies • 13646 views
  • Discussion

    simulating for sigma delta noise folding due to charge pump nonlinearity

    Category: Custom IC Design

    By vamshiky vamshiky

    •

    updated over 11 years ago by Andrew Beckett

    5 replies • 15593 views
  • Discussion

    Modify netlist of a block and resimulate (CDL.... CDF....)

    Category: Custom IC Design

    By cozdag cozdag

    •

    updated over 11 years ago by Andrew Beckett

    1 replies • 17257 views
  • Discussion

    Get run mode in ADEXL prerun script

    Category: Custom IC Design

    By webbyguy webbyguy

    •

    updated over 11 years ago by Andrew Beckett

    2 replies • 13375 views
  • Discussion

    Virtuoso XL generate>selected from source issue

    Category: Custom IC Design

    By Roopak25 Roopak25

    •

    updated over 11 years ago by gabriel rf

    6 replies • 5513 views
  • Discussion

    layout connection problem in virtuoso layout XL

    Category: Custom IC Design

    By whitefan whitefan

    •

    updated over 11 years ago by whitefan

    2 replies • 13789 views
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