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Custom IC Design

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  • Discussion

    Spectre warning: there are some nodes and instances from the netlist topology check.

    Category: Custom IC Design

    By ppptt ppptt

    •

    updated over 2 years ago by Andrew Beckett

    1 replies • 6642 views
  • Discussion

    PVS fails with version `GLIBCXX_3.4.26' not found

    Category: Custom IC Design

    By thspaet thspaet

    •

    updated over 2 years ago by thspaet

    3 replies • 2999 views
  • Discussion

    setting cell's view in config as dynamic parameter

    Category: Custom IC Design

    By sjwprcker sjwprcker

    •

    updated over 2 years ago by sjwprcker

    2 replies • 1307 views
  • Discussion

    BJT models HiCUM (bht)

    Category: Custom IC Design

    By sidm sidm

    •

    updated over 2 years ago by sidm

    6 replies • 7780 views
  • Discussion

    DRC check and LVS check has no error but still seeing the layer error?

    Category: Custom IC Design

    By Vishesh Gupta Vishesh Gupta

    •

    updated over 2 years ago by Andrew Beckett

    1 replies • 5963 views
  • Discussion

    Setting dynamic parmeter in pss analysis

    Category: Custom IC Design

    By Abhrarup Abhrarup

    •

    updated over 2 years ago by Andrew Beckett

    1 replies • 6060 views
  • Discussion

    Maestro : Width of columns in "Results" Tab is large. How to reduce it?

    Category: Custom IC Design

    By Saikiran IND Saikiran IND

    •

    updated over 2 years ago by Saikiran IND

    2 replies • 1426 views
  • Discussion

    Maestro: Simulation Settings as Output Expressions

    Category: Custom IC Design

    By Saikiran IND Saikiran IND

    •

    updated over 2 years ago by Saikiran IND

    2 replies • 6654 views
  • Discussion

    The region of operation of MOS transistor

    Category: Custom IC Design

    By PhD Student PhD Student

    •

    updated over 2 years ago by PhD Student

    12 replies • 13170 views
  • Discussion

    Simulation startup is too slow

    Category: Custom IC Design

    By Firdos Firdos

    •

    updated over 2 years ago by ShawnLogan

    1 replies • 6414 views
  • Discussion

    rexMatchp error when netlist

    Category: Custom IC Design

    By sjwprcker sjwprcker

    •

    updated over 2 years ago by Andrew Beckett

    1 replies • 6433 views
  • Discussion

    Ramp signal generator in Verilog-A

    Category: Custom IC Design

    By delgsy delgsy

    •

    updated over 2 years ago by ShawnLogan

    1 replies • 9118 views
  • Discussion

    Post Trimming Simulation for Oscillator Circuit

    Category: Custom IC Design

    By yoshi777 yoshi777

    •

    updated over 2 years ago by ShawnLogan

    8 replies • 10276 views
  • Discussion

    design/global variables import from veilogA

    Category: Custom IC Design

    By Majco Majco

    •

    started over 2 years ago

    0 replies • 812 views
  • Discussion

    Pixelate Custom Curved Polygon According to Grid in Virtuoso Layout Suite L

    Category: Custom IC Design

    By Herramar Herramar

    •

    updated over 2 years ago by Andrew Beckett

    3 replies • 6958 views
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