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Stacked Vias

Davadaroo Baba

Hi,

I am interested to know if these's a way to create a stacked VIA, say a stack of VIA4 & VIA5 in a 6 metal process.

I am interested to know  how do I add this Stack VIA in the technology file? Can I add it to the tech file throught an API like the CreateStdVia & the CreateCustomVia? Or should I specify it in a constarain group entry(desired one),

I need Via4 & VIA5 placed one over the other.

 

Thanks in Advance.

 

Krish

 

Parents

  • Setup a customViaDef which defines a via M6_M4 between M4 and M6.

     Create a pcell M6_M4 which draws the necessary layers for the via. It could check the valid layer list and not draw M5 or it could always draw V4, M5, V5 but the designer would not be able to route on M5 because it is not in the valid layer list. The pcell would have the parameters which coorespond to the stdViaDef parameters so the tools would place them correctly on wide wires.

    Create two  constraint groups, with and without M5 and use the appropriate one.

    ( "Design_With_M5_group"    nil
        interconnect(
         ( validLayers   (NW OD PO1 M1 M2 M3 M4 M5 M6 .....  ) )
         ( validVias     ( M1__PO M2_M1 M3_M2 M4_M3 M5_M4 M6_M5 ))
        ) ;interconnect
      ) ;

    ( "Design_Without_M5_group"    nil
        interconnect(
         ( validLayers   (NW OD PO1 M1 M2 M3 M4 M6 .....  ) )
         ( validVias     ( M1__PO M2_M1 M3_M2 M4_M3 M6_M4  ))
        ) ;interconnect
      ) ;

    When a designer finds the need for M5, they just switch constraint groups. The cell would still exist in the current library and would draw the appropriate layers.

Reply

  • Setup a customViaDef which defines a via M6_M4 between M4 and M6.

     Create a pcell M6_M4 which draws the necessary layers for the via. It could check the valid layer list and not draw M5 or it could always draw V4, M5, V5 but the designer would not be able to route on M5 because it is not in the valid layer list. The pcell would have the parameters which coorespond to the stdViaDef parameters so the tools would place them correctly on wide wires.

    Create two  constraint groups, with and without M5 and use the appropriate one.

    ( "Design_With_M5_group"    nil
        interconnect(
         ( validLayers   (NW OD PO1 M1 M2 M3 M4 M5 M6 .....  ) )
         ( validVias     ( M1__PO M2_M1 M3_M2 M4_M3 M5_M4 M6_M5 ))
        ) ;interconnect
      ) ;

    ( "Design_Without_M5_group"    nil
        interconnect(
         ( validLayers   (NW OD PO1 M1 M2 M3 M4 M6 .....  ) )
         ( validVias     ( M1__PO M2_M1 M3_M2 M4_M3 M6_M4  ))
        ) ;interconnect
      ) ;

    When a designer finds the need for M5, they just switch constraint groups. The cell would still exist in the current library and would draw the appropriate layers.

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