Stacked Vias

Which version are you using? The answer is different between IC5141 and IC613.

Regards,

Andrew

Andrew,

I am using 6.1.3

Thanks

Regards

Hi Krish,

In that case, you should use Create->Via and then select "Stack" and you can enter the start and stop layers. It will create a stack of vias. Yes, it's multiple via objects, each of which is between a pair of layers, but this has the advantage of being simpler, and also better understood by multiple tools.

If  you use create wire, and change through multiple layers (e.g. hit the space bar to change layer), it will place a stack of vias for you.

Also, in the "Options" toolbar there is an icon to control whether Via Stack selection is on or not (this also appears on the Options->Selection form). What this does is ensure that if you click on a stack of vias, it selects the entire stack, rather than just the individial vias.

So there really is no need (and indeed it's not recommended) to create specific stacked vias in the tech file.

Regards,

Andrew.

 Hi Andrew,

This is the exact way I am following now.

But I  am trying to  get  the following mechanism work :

( "Dummy_via_group"    nil
    interconnect(
     ( validLayers   (NW OD PO1 M1 M2 M3 M4 M6 .....  ) )
     ( validVias     ( M1__PO M2_M1 M3_M2 M4_M3 M5_M4 M6_M5 ))
    ) ;interconnect
  ) ;

If I select the  following via group and create a wire,  when I move from M4 to up , it mus place  a stacked Via containing M5_M4_VIA & M6_M5_VIA

What  changes do I do in the technology file if needed  to achieve this.

Thanks

You don't have M5 in the valid layers. If you have M5 in the valid layers, you can hop from M4 to M6 and it should put both vias in, as a stack.

Regards,

Andrew.

 M5 in my case becomes an invalid routing layer and will be not available.

There are 2 cases.

#1. Process XYZ Where M1, M2, M3, M4, M5 & M6 are available and it puts up a stack, everything works great

#2. Process ABC Where only M5 is absent and this is where I face the problem. Especially when I want to  have design portability between the 2 options.

Krish,

If M5 is absent in the process, don't you just need to define an M4_M6 via - it's not going to be stacked, because there's no M5? Or have I misunderstood? I can't see how you could have a stack from M4 to M5, then M5 to M6 if there's no M5 in the process...

Regards,

Andrew.

 Yes M5 is absent in this process option .

If I have M6_M4 Via I will face a major issue in porting this desigh to the process option where M5 is present. Because there we do not have a Via M6_M4 obviously.

Any design using this M6_M4 via will not be portable in the process option with  M5 present.

Setup a customViaDef which defines a via M6_M4 between M4 and M6.

 Create a pcell M6_M4 which draws the necessary layers for the via. It could check the valid layer list and not draw M5 or it could always draw V4, M5, V5 but the designer would not be able to route on M5 because it is not in the valid layer list. The pcell would have the parameters which coorespond to the stdViaDef parameters so the tools would place them correctly on wide wires.

Create two  constraint groups, with and without M5 and use the appropriate one.

( "Design_With_M5_group"    nil
    interconnect(
     ( validLayers   (NW OD PO1 M1 M2 M3 M4 M5 M6 .....  ) )
     ( validVias     ( M1__PO M2_M1 M3_M2 M4_M3 M5_M4 M6_M5 ))
    ) ;interconnect
  ) ;

( "Design_Without_M5_group"    nil
    interconnect(
     ( validLayers   (NW OD PO1 M1 M2 M3 M4 M6 .....  ) )
     ( validVias     ( M1__PO M2_M1 M3_M2 M4_M3 M6_M4  ))
    ) ;interconnect
  ) ;

When a designer finds the need for M5, they just switch constraint groups. The cell would still exist in the current library and would draw the appropriate layers.