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Stop Simulation by Itself

gilberts

Is there a way to stop a simulation after a certain condition have been met? - ( VerilogA maybe? )

 

Example:

I setup a transient simulation to run for 50m secons.

The circuit oscillates for an unknown frequency, can be too high or too low.

In an alter, when the frequency is too high, the simulation time gets too long

and the results are not anymore necessary.

I only need to complete 20 cycles to analyze the results,

so I want to force stop/kill the simulation after completing 20 cycles on the output.

 

Thanks.

Gilbert

Parents
  • Andrew Beckett

    Hi Gilbert,

    This is the kind of thing that can be done with Spectre MDL, but a VerilogA based solution is quite reasonable too. You could use $finish or $finish_current_analysis for this.

    See SourceLink Solutions 11556554 and 11488490.

    Regards,

    Andrew.

  • HoWei
    in reply to Andrew Beckett

    Hi Andrew,

    the above links are broken.

    Can you please add a working link or post a solution here ?

    I need to do the same thing as Gilbert, but I want to do it in ADE-Assembler.

    BR

    Holger

Reply
  • HoWei
    in reply to Andrew Beckett

    Hi Andrew,

    the above links are broken.

    Can you please add a working link or post a solution here ?

    I need to do the same thing as Gilbert, but I want to do it in ADE-Assembler.

    BR

    Holger

Children
  • Andrew Beckett
    in reply to HoWei

    Hi Holger,

    I've fixed them.

    Andrew.

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