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  3. Stop Simulation by Itself

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Stop Simulation by Itself

gilberts
gilberts over 15 years ago

Is there a way to stop a simulation after a certain condition have been met? - ( VerilogA maybe? )

 

Example:

I setup a transient simulation to run for 50m secons.

The circuit oscillates for an unknown frequency, can be too high or too low.

In an alter, when the frequency is too high, the simulation time gets too long

and the results are not anymore necessary.

I only need to complete 20 cycles to analyze the results,

so I want to force stop/kill the simulation after completing 20 cycles on the output.

 

Thanks.

Gilbert

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  • Andrew Beckett
    Andrew Beckett over 15 years ago

    Hi Gilbert,

    This is the kind of thing that can be done with Spectre MDL, but a VerilogA based solution is quite reasonable too. You could use $finish or $finish_current_analysis for this.

    See SourceLink Solutions 11556554 and 11488490.

    Regards,

    Andrew.

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  • gilberts
    gilberts over 15 years ago

    Andrew,

    Thank you very much.

     

    Best regards,

    Gilbert

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  • HoWei
    HoWei over 4 years ago in reply to Andrew Beckett

    Hi Andrew,

    the above links are broken.

    Can you please add a working link or post a solution here ?

    I need to do the same thing as Gilbert, but I want to do it in ADE-Assembler.

    BR

    Holger

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  • Andrew Beckett
    Andrew Beckett over 4 years ago in reply to HoWei

    Hi Holger,

    I've fixed them.

    Andrew.

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  • HoWei
    HoWei over 4 years ago in reply to Andrew Beckett

    Hi,

    I was able to get it to work with a VerilogA-model.

    Now the question is - can the same thing be done via output-expressions in ADE-Assembler ?

    Are those output expressions evaluated during runtime or only at the end of the simulation ?

    BR

    Holger

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  • Andrew Beckett
    Andrew Beckett over 4 years ago in reply to HoWei

    Holger,

    They're only evaluated at the end of simulation, so there's no mechanism for them to stop simulations part way through. The only way to do that is to use either the Verilog-A approach, or using MDL to control the simulation and use the auto-stop mechanism with Spectre MDL (MDL doesn't entirely play nicely with ADE since you effectively have a different simulation control mechanism, although it can be done...). I'd probably use the Verilog-A approach.

    Andrew.

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  • ebecheto
    ebecheto over 4 years ago in reply to HoWei

    Dear HoWei,

    With ADE-L, you could just put in the field : "stopTime" the following text : VAR("T")

    Then, in the Design Variable, you can add for instance :

    Name | Value

    -------------

    fr         |   10k

    T         |  2/fr

    With this configuration, your parametric simulation will show only two periode of you vsin for instance, and stop "correctly" the simulation after the two periode.

    Hope it helps,

    Regards,

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  • drdanmc
    drdanmc over 4 years ago in reply to Andrew Beckett

    In the first of those links it says:

    "1. $finish_current_analysis should only be used with transient and pss analysis. It should not be used during ac analysis."

    could you expand on that?  I've only ever used this trick (Verilog-A to stop a simulation early) with transient analysis but since $finish is like a hard stop (including additional analysis) I avoid it.  But then again I'm not sure what event could be triggered in an AC analysis anyway.

    Adding this onto this thread in case others get here searching for $finish/$finish_current_analysis.

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  • Andrew Beckett
    Andrew Beckett over 4 years ago in reply to drdanmc
    drdanmc said:
    could you expand on that?

    The reason is that when you do a small-signal analysis, it's not really executing the code in the model during the analysis. Instead, the circuit is linearised using the equations in the model at the beginning of the analysis (although that may happen at other points during the sweep too if something other than frequency is swept in the ac analysis which results in a different operating point), and then it simulates the linear model. So the sequential code in the model doesn't get run and hence there wouldn't be an opportunity to trigger something to $finish/$finish_current_analysis.

    Andrew.

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  • Frank Wiedmann
    Frank Wiedmann over 4 years ago in reply to Andrew Beckett

    So maybe the article should rather say "It will not be effective during ac analysis."

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