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Stop Simulation by Itself

gilberts

Is there a way to stop a simulation after a certain condition have been met? - ( VerilogA maybe? )

 

Example:

I setup a transient simulation to run for 50m secons.

The circuit oscillates for an unknown frequency, can be too high or too low.

In an alter, when the frequency is too high, the simulation time gets too long

and the results are not anymore necessary.

I only need to complete 20 cycles to analyze the results,

so I want to force stop/kill the simulation after completing 20 cycles on the output.

 

Thanks.

Gilbert

Parents
  • Andrew Beckett

    Hi Gilbert,

    This is the kind of thing that can be done with Spectre MDL, but a VerilogA based solution is quite reasonable too. You could use $finish or $finish_current_analysis for this.

    See SourceLink Solutions 11556554 and 11488490.

    Regards,

    Andrew.

  • HoWei
    in reply to Andrew Beckett

    Hi,

    I was able to get it to work with a VerilogA-model.

    Now the question is - can the same thing be done via output-expressions in ADE-Assembler ?

    Are those output expressions evaluated during runtime or only at the end of the simulation ?

    BR

    Holger

  • Andrew Beckett
    in reply to HoWei

    Holger,

    They're only evaluated at the end of simulation, so there's no mechanism for them to stop simulations part way through. The only way to do that is to use either the Verilog-A approach, or using MDL to control the simulation and use the auto-stop mechanism with Spectre MDL (MDL doesn't entirely play nicely with ADE since you effectively have a different simulation control mechanism, although it can be done...). I'd probably use the Verilog-A approach.

    Andrew.

Reply
  • Andrew Beckett
    in reply to HoWei

    Holger,

    They're only evaluated at the end of simulation, so there's no mechanism for them to stop simulations part way through. The only way to do that is to use either the Verilog-A approach, or using MDL to control the simulation and use the auto-stop mechanism with Spectre MDL (MDL doesn't entirely play nicely with ADE since you effectively have a different simulation control mechanism, although it can be done...). I'd probably use the Verilog-A approach.

    Andrew.

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