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[Cadence Virtuoso] matching schematic transistors with interdigitated layout counterparts

calbear2009

Hi,

In Cadence Virtuoso/Composer, I am trying to match multiple transistors devices in my schematic to interdigitated transistors in layout.

However, Virtuoso seems to have a problem mapping many schematic devices to a single cell in layout. How do I do this? This would be crucial for LVS, and I believe the interdigitated fingers for matching transistors is a common practice. Thanks a lot in advance!

Parents

  • I had a bunch of transistor devices in schematic, but combined them as one transistor cell in layout (with multiple fingers).

    I realized this is probably the toughest way to go.

    Instead, I generated a transistor cell in layout for each transistor in schematic, and then overlapped the source or drains

    of each transistor layout cell with another to create the interdigitation I desired. This fixed the problem I had, and the cells were

    already mapped between schematic and layout.

    I guess this is why cadence will not let me map one layout device to multiple schematic devices, since no one would do something dumb like I did. Thank you very much for helping me along the way.

Reply

  • I had a bunch of transistor devices in schematic, but combined them as one transistor cell in layout (with multiple fingers).

    I realized this is probably the toughest way to go.

    Instead, I generated a transistor cell in layout for each transistor in schematic, and then overlapped the source or drains

    of each transistor layout cell with another to create the interdigitation I desired. This fixed the problem I had, and the cells were

    already mapped between schematic and layout.

    I guess this is why cadence will not let me map one layout device to multiple schematic devices, since no one would do something dumb like I did. Thank you very much for helping me along the way.

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