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Problem in simulation by integrating Random generator with other analog blocks

Analog Design

 Hi ,

 I want to do simulation after integrating  Random generator(Designed in Verilog-A) with other analog blocks. Indivual simulation of Random generator takes less time and gives output within fraction of second . But after integration with other  analog modules(Designed by devices from UMC180nm libraries) , spectre simulator contineously running without completion of simulation. After Some time  It seems to be no completion of simulation ,so I have to  stop simulation before completion . How to overcome this  problem (to complete simulation)? I am donig simulation in Cadence spectre(version ICv5.1)

The design Code like below

`include "discipline.h"
`include "constants.h"

module noise_src(vout,ref);
output vout;
input ref;
electrical vout,ref;
parameter real amp = 0.2 from [0:inf);
parameter real att = 10 from [0:inf);
integer seed;

analog begin
@ (initial_step) begin
seed=23;
end

V(vout,ref) <+ amp * $dist_normal(seed,0,1)/att;
$display ("seed is %d",seed);
end

endmodule

  • The problem is that you have a model which is not well written. It is changing the output voltage in a discontinuous fashion at each timestep. Because the amplitude of the change is quite large, the simulator tries to handle this discontinuity (particularly as seen by the circuit connected to this noise source) by putting some additional points around the transition to try to follow it better - assuming (incorrectly) that by adding more points it will be smoother. What then happens is that you get even more random numbers, and hence more discontinuity over a shorter time, and so on - resulting in it (probably) zooming in to take very short timesteps.

    Fundamentally discontinuities are bad  (especially such large ones - your amplitude here is 0.02 V by default), and so you really need to have something to smooth out those transitions. Real life does not have instantaneous changes - and circuit simulators are not designed to be able to completely cope with such unrealistic changes (although a lot of effort has gone in to reduce the impact). Some thoughts as to how to resolve this:

    1. Use @(timer(...)) to schedule the random number to be updated on a regular (but fixed) timestep - this means you are not altering the timestep based on your random number generation
    2. Then use the transition() function to give a sensible transition between the values. Or maybe slew() to slew rate limit the changes, or  use one of the laplace functions to filter the discrete changes into a smoother form.

    Regards,

    Andrew.

  • Hi Andrew,

    Thank you for help . I am using UMC 180nm library models for devices(PMOS,NMOS,Resistors ..etc) used for analog circuits and acessing sources for analogLib and using cadence spectre simulator . Can you give some time for me ,that is whrere and what are modification have to done in my verilog-A code what is posted in forum(Analog Design). Because I am not sound enough in verilog-A .

  • I'm afraid I don't have the bandwidth to write the model for you. It would probably make sense to read a good book on Verilog A, such as The Designer's Guide to Verilog-AMS

    BTW, how are you replying to posts? Every time you reply, the email notifier is scrambled, and it ends  up as a separate thread (I have to keep going in and merging them). Which web browser are you using (is it Chrome? Because there are known issues with Chrome with this forum).

    Regards,

    Andrew.

  • Hi Andrew ,

                    I did not got why you afraid?  .Anyway by using timer()  ,I am able to generate random sequence and  integrate  with other modules . Thanks for idea .

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