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Problem in simulation by integrating Random generator with other analog blocks

Analog Design

 Hi ,

 I want to do simulation after integrating  Random generator(Designed in Verilog-A) with other analog blocks. Indivual simulation of Random generator takes less time and gives output within fraction of second . But after integration with other  analog modules(Designed by devices from UMC180nm libraries) , spectre simulator contineously running without completion of simulation. After Some time  It seems to be no completion of simulation ,so I have to  stop simulation before completion . How to overcome this  problem (to complete simulation)? I am donig simulation in Cadence spectre(version ICv5.1)

The design Code like below

`include "discipline.h"
`include "constants.h"

module noise_src(vout,ref);
output vout;
input ref;
electrical vout,ref;
parameter real amp = 0.2 from [0:inf);
parameter real att = 10 from [0:inf);
integer seed;

analog begin
@ (initial_step) begin
seed=23;
end

V(vout,ref) <+ amp * $dist_normal(seed,0,1)/att;
$display ("seed is %d",seed);
end

endmodule
Parents
  • Analog Design

    Hi Andrew ,

                    I did not got why you afraid?  .Anyway by using timer()  ,I am able to generate random sequence and  integrate  with other modules . Thanks for idea .

Reply
  • Analog Design

    Hi Andrew ,

                    I did not got why you afraid?  .Anyway by using timer()  ,I am able to generate random sequence and  integrate  with other modules . Thanks for idea .

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