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Programm a verilog block to stop simulation.

Hi all,

Is there any possibility to have a verilog block and programme it to finish a simulation when - for instance- his input is on ? It's to save time during corner analysis:

If a signal cross 0V at 10ms, i run simulation for 20ms for covers process variation, so Can I stop automatically the simulation with a verilog block without create an error ?

Thanks,

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Andrew Beckett over 14 years ago

You cannot use ADE expressions inside VerilogA, but coding a similar check would be trivial in VerilogA.
Regards,
Andrew.
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Andrew Beckett over 14 years ago

You cannot use ADE expressions inside VerilogA, but coding a similar check would be trivial in VerilogA.
Regards,
Andrew.
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