Help on checking Spacing between two layers and probe it when space is less than minimum.

Could you not use DRD (Design Rule Driven) capabilities built into the tool to do this rather than inventing your own wheel?

Regards,

Andrew.

 Thanks Andrew for replay. Now we are working on a process(rulefiles supported to Dracula which is at some other server) which doesnot had a rulefile to run Assura DRC. So we convert layout into gds file and run Dracula at some other Server. So now I need to write rules for DRC. Can I write rule file? 

 I'm not suggesting you write an Assura DRC rule file. The DRD capability uses the minSpacing, minWidth type properties/rules in the technology file - so you'd have to ensure your tech file is suitably populated with such rules.

The rules of DRD (particularly in IC5141; IC615 has a richer set) are rather simpler than full-blown DRC,  but for simple wire spacing, it's usually sufficient. The documentation will help you to understand what you need to do...

Regards,

Andrew.

 hi Andrew,

                DRD works min spacing & minwidth. Now i need to check enclosure ( like min enclose NWELL should be 4um on DIFF ). Is there any commands to 1) get enclosure value of 1st object on second object ? 2) Overlap value between two layers and its pionts.

       And   Can i fix any rules  in DRD?.(Because it shows marker when MET2 to MET2 1.2um But I want marker at 2um)

DRD also supports minEnclosure. For example, in my gpdk090 technology file from IC5141 I have:

orderedSpacingRules(
 ;( rule                    layer1        layer2        value    )
 ;( ----                    ------        ------        -----    )
  ( minEnclosure            "Metal1"        "Cont"        0.0     )
  ( minEnclosure            "Oxide"        "Poly"        0.2     )
  ( minEnclosure            "Nimp"        "Oxide"        0.14     )
  ( minEnclosure            "Nimp"        "Poly"        0.18     )
  ( minEnclosure            "Pimp"        "Poly"        0.12     )
  ( minEnclosure            "Pimp"        "Oxide"        0.18     )
  ( minEnclosure            "Nwell"        "Oxide"        0.14     )
...
)

And DRD can check that my Nwell is sufficiently overlapping the Oxide (i.e. Diffusion).

Regards,

Andrew.

  Thanks Andrew. I wrote some physicalRules(I didn't save it in techfile) through CIW -> tools ->Technology File Manager...->EditRules. I need to apply these changed rules for DRD every time when invoked into LayoutXL or LayoutTurboEditing. For that I save(save option in DRD) modified values of DRD in a file. 

          When I invoked into LayoutTurboEditing and then load that file into DRD rule options then it shows.

 *WARNING* DRDEdit: Unable to define new rule due to missing rule value: (("NWELL" "all") ("BL" "all") "minEnclosure" t "y0" nil "" (t "global"))

I was unable to execute with previous values & spacings.

The defined rules for DRD are cached (at least from my experiments), so you must make any changes to the tech file before you open layout XL and bring up the DRD Rules form. If you make the changes and then open the layout and bring up the form, you'll see the new rules present - you don't need to use the save or load options to make them visible.

You can't make them appear by saving a file, editing it, and re-loading - this mechanism is to allow you to enable and disable existing rules, not make them appear or not.

I saw the same problem you did if I'd previously brought up the DRD forms and then tried to load a file where I'd edited in the new rule combination.

The best thing is just to update the tech file, and then everything is clean.

Andrew.

Thanks Andrew,

                      I followed as you suggested in last post. I defined no.of rules in my techfile through CIW->Tools->technology file manager. I don't know can I save it or not. If I not saving this to my techfile then these rules are works untill not exiting from CIW. So now i need to load file that will set my rules when I need it.

I need to edit the my tech file to define cdsVia's. But my techfile in Ascii format. I need to convert it to Skill format. Can you please help me?

Venu,

I don't really know what you mean by a tech file in "SKILL format". If you're looking for a SKILL way to create the cdsViaDevice definitions, I don't believe that exists in IC5141 (there are techCreate.* functions in IC61, but not in IC5141).

You can always use tcLoadTechFile() to merge or replace a part of the technology database from an ASCII file - so you could put the section you wish to compile in a file, and then use tcLoadTechFile to load it.

Regards,

Andrew