How to use Cadence example in cadence_inst/tools.lnx86/dfII/samples/ROD/rodPcells for auto abutment?

I just tried the simplemos devices from the sample pcells, and abutment works for me. Maybe something in your environment has turned off abutment in VLS XL?

Not sure which version you're using, but in IC615 in VLS XL you can do Options->Layout XL and then on the Generation tab is "Abut transistors" turned on?

I'm not really familiar with recent PDKs from XFAB or Tower, but I'd be surprised if they don't support abutment. It would certainly be worth checking with them.

Regards,

Andrew.

I just tried this in IC5141, and it worked for me there too. Here's what I did:

1. Created myself a library (compiled using the same tech file as gpdk090 - but that doesn't matter too much). 
2. Loaded the sample pcell code:
   setSkillPath(prependInstallPath("samples/ROD/rodPcells"))
   load("install/spcLoadInstall.il")
3. Picked the Sample Pcells->Install menu in the CIW, and filled things in. Just enabled the simple mos devices, and completed a few missing layers and rules.
4. Copied nmos4/symbol from analogLib to mypcells/spcsimple_nmos/symbol
5. Created a simple schematic with some series connected devices (I assume you did this, because it needs to know that to understand how they are abutted).
6. Started layout XL
7. Did a gen from source
8. Moved the instances around so the source/drains overlapped and watched them about.

In the attached picture, you'll see that two of the devices have a shared source drain with no third connection, and one has a pin too - so the metal will remain. I've cross-selected between the schematic and layout so you can see which device is which.

Regards,

Andrew.

Is it possible to tar up your library (tar cvfz data.tgz yourLib) and upload it? (please make sure it's small and doesn't contain extraneous junk before you do). Otherwise I think you'll need to log a service request via Cadence Online Support.

The setSkillPath() bit isn't important here - that was just me avoiding copying the code.

Regards,

Andrew.

OK, I've taken a look at your data.

First of all, I'm not convinced the right layers have been used in the pcells. I'm having to guess a bit because I'm not familiar with the layer names in the technology, but the diffusion layer used in the pcells is "NN" or "PP" (for NMOS or PMOS devices respectively). Taking a look at the technology file, my guess is that NN and PP are the implant layers, and "AA" is the diffusion (aka "active") layer. That said, in some places in the tech file it is marked as a diffusion layer, sometimes as a local interconnect - so it's not that clear what is supposed to be correct.

The reason why the abutment doesn't work is because the sample pcell devices get created with the abutment properties on the "diffusion" pins on the source and drain. The source and drain actually have two pins each; one for the metal, and one for the "diffusion" (so "NN" or "PP" in your case as you've selected them). The abutment properties only get added on the pins which are diffusion, because they need to be there all the time - and a consequence of abutment is that the metal pins might get turned off - so abutment is triggered based on connectivity on the diffusion layers.

In your tech file you have:

lxRules(

 lxExtractLayers(
 ;( list of layers or layer/purpose pairs  )
 ;( -------------------------------------  )
  ( P1            P2            CO            M1            V1            M2            V2            M3         )
 ) ;lxExtractLayers
...
)

The layers used for the diffusion pins are not listed. Because of that, Layout XL is not concerned with connectivity on the layers forming the "diffusion" pins - and so nothing will trigger abutment. If I update the lxExtractLayers to the following:

lxRules(

 lxExtractLayers(
 ;( list of layers or layer/purpose pairs  )
 ;( -------------------------------------  )
  ( P1            P2            NN PP CO            M1            V1            M2            V2            M3         )
 ) ;lxExtractLayers
...
)

Then abutment works. Of course, if it's really supposed to be "AA" that you used for the diffusion layer, you'd put "AA" in that list instead - and make your pcells use this as the diffusion layer. 

I may be completely wrong about the "AA" versus "NN"/"PP" layer in your technology, but at the very least whatever layer you use as the diffusion layer needs to be in the lxExtractLayers for abutment to work with the sample pcells.

Regards,

Andrew.