Stats

  • Locked Locked
  • Replies 8
  • Subscribers 142
  • Views 4181
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

How to use Cadence example in cadence_inst/tools.lnx86/dfII/samples/ROD/rodPcells for auto abutment?

TiNat
Hi, I have used PDK of XFAB (Germany Company) and Tower (Israeli Company).But recently in vlxhelp.pdf I have found an auto abutment capability in Layout XL. Unfortunately, neither XFAB Pcells nor Tower Pcells don't have such capability. I want to create my own Pcell with auto abutment ability. Firs of all I want to see how auto abutment look in practice. It is a good thing that Cadence has an example in cadence_inst/tools.lnx86/dfII/samples/ROD/rodPcells. I have install simple_mos components, copy symbol view nmos4 from analogLib. But auto abutment doesn't run. What is the matter? Skill file simple_mos.il contains abutment block. Where was I mistaken? Regards.
Parents

  • I just tried this in IC5141, and it worked for me there too. Here's what I did:

    1. Created myself a library (compiled using the same tech file as gpdk090 - but that doesn't matter too much). 
    2. Loaded the sample pcell code:
      setSkillPath(prependInstallPath("samples/ROD/rodPcells"))
      load("install/spcLoadInstall.il")
    3. Picked the Sample Pcells->Install menu in the CIW, and filled things in. Just enabled the simple mos devices, and completed a few missing layers and rules.
    4. Copied nmos4/symbol from analogLib to mypcells/spcsimple_nmos/symbol
    5. Created a simple schematic with some series connected devices (I assume you did this, because it needs to know that to understand how they are abutted).
    6. Started layout XL
    7. Did a gen from source
    8. Moved the instances around so the source/drains overlapped and watched them about.

    In the attached picture, you'll see that two of the devices have a shared source drain with no third connection, and one has a pin too - so the metal will remain. I've cross-selected between the schematic and layout so you can see which device is which.

    Regards,

    Andrew.

Reply

  • I just tried this in IC5141, and it worked for me there too. Here's what I did:

    1. Created myself a library (compiled using the same tech file as gpdk090 - but that doesn't matter too much). 
    2. Loaded the sample pcell code:
      setSkillPath(prependInstallPath("samples/ROD/rodPcells"))
      load("install/spcLoadInstall.il")
    3. Picked the Sample Pcells->Install menu in the CIW, and filled things in. Just enabled the simple mos devices, and completed a few missing layers and rules.
    4. Copied nmos4/symbol from analogLib to mypcells/spcsimple_nmos/symbol
    5. Created a simple schematic with some series connected devices (I assume you did this, because it needs to know that to understand how they are abutted).
    6. Started layout XL
    7. Did a gen from source
    8. Moved the instances around so the source/drains overlapped and watched them about.

    In the attached picture, you'll see that two of the devices have a shared source drain with no third connection, and one has a pin too - so the metal will remain. I've cross-selected between the schematic and layout so you can see which device is which.

    Regards,

    Andrew.

Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.