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Is there any way to generate verilog(not verilog-A) netlist from schematic with SKILL or other batch

clker1

I know how to generate it with verilog-XL simulator. But I want to use script but not GUI to do this. I hate click click and click again.

Can you help me? 

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  • In the run directory that you specified in the si command. There's not a single netlist by default - but there is a file listing all the input files that need to be passed to the simulator.

    There is a variable you can set to tell it to concatenate everything (at least to concatenate all the modules netlisted from schematics etc - the modules which came from textual views are not merged into this single file). This could go in various places, including your .simrc file:

    vlogifCompatibilityMode="4.0"

    Search on for this variable for more details.

    Regards,

    Andrew.

Reply

  • In the run directory that you specified in the si command. There's not a single netlist by default - but there is a file listing all the input files that need to be passed to the simulator.

    There is a variable you can set to tell it to concatenate everything (at least to concatenate all the modules netlisted from schematics etc - the modules which came from textual views are not merged into this single file). This could go in various places, including your .simrc file:

    vlogifCompatibilityMode="4.0"

    Search on for this variable for more details.

    Regards,

    Andrew.

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