List of symbol pin names and direction using SKILL

Hi Andrew, I try to get the accessDir of my different pin from my symbol cell. Because i try to create automaticelly a verilog file for creating a schematic decoder who use my logic cell. So i must to have the differents pins from my symbol and the direction ( left right top bottom) because i need the CORECT order of my pins => DVDDBIPBIP must to connect to DVDDDBIPBIP and not AB[6]. Actually I use that for having the order => cv~>nets~>term~>name / but it's not the good order of my pins. When i create a symbol from my schematic i put some pins in the left list some pins in the right list... so the order pin is different and i think i could find the order if i find the pointer on this diffrent list ( left right...) but there is nothing in cv~>lpps~>shapes~>pin~>accessDir... so i don't understant how cadence manage the order to connect the pin when it use a verilog file. Do you know ? 

Exemple :  

module AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAATST_1_131(XBIPBIP, ABIP, AB, DVSSBIPBIP, DVDDBIPBIP);

output[131:1] XBIPBIP;

input[11:2] ABIP;

input[11:2] AB;

input DVSSBIPBIP, DVDDBIPBIP;

AAA_COL1U1SRAM_ADD_DEC cell1(  XBIPBIP[1],   ABIP[2],   AB[3],   AB[4],   AB[5],   AB[6],   AB[7],   AB[8],   AB[9],   AB[10],   AB[11], DVDDBIPBIP, DVSSBIPBIP );

AAA_COL1U1SRAM_ADD_DEC cell2(  XBIPBIP[2],   ABIP[2], ABIP[3],   AB[4],   AB[5],   AB[6],   AB[7],   AB[8],   AB[9],   AB[10],   AB[11], DVDDBIPBIP, DVSSBIPBIP );

Hi Andrew, I try to get the accessDir of my different pin from my symbol cell. Because i try to create automaticelly a verilog file for creating a schematic decoder who use my logic cell. So i must to have the differents pins from my symbol and the direction ( left right top bottom) because i need the CORECT order of my pins => DVDDBIPBIP must to connect to DVDDDBIPBIP and not AB[6]. Actually I use that for having the order => cv~>nets~>term~>name / but it's not the good order of my pins. When i create a symbol from my schematic i put some pins in the left list some pins in the right list... so the order pin is different and i think i could find the order if i find the pointer on this diffrent list ( left right...) but there is nothing in cv~>lpps~>shapes~>pin~>accessDir... so i don't understant how cadence manage the order to connect the pin when it use a verilog file. Do you know ? 

Exemple :  

module AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAATST_1_131(XBIPBIP, ABIP, AB, DVSSBIPBIP, DVDDBIPBIP);

output[131:1] XBIPBIP;

input[11:2] ABIP;

input[11:2] AB;

input DVSSBIPBIP, DVDDBIPBIP;

AAA_COL1U1SRAM_ADD_DEC cell1(  XBIPBIP[1],   ABIP[2],   AB[3],   AB[4],   AB[5],   AB[6],   AB[7],   AB[8],   AB[9],   AB[10],   AB[11], DVDDBIPBIP, DVSSBIPBIP );

AAA_COL1U1SRAM_ADD_DEC cell2(  XBIPBIP[2],   ABIP[2], ABIP[3],   AB[4],   AB[5],   AB[6],   AB[7],   AB[8],   AB[9],   AB[10],   AB[11], DVDDBIPBIP, DVSSBIPBIP );