I want to get a list of pins names and which direction the pins have from a symbol/schematic. I guess SKILL is the way to go? I new to SKILL, so if someone could push me in the right direction I would be grateful:)
Okay, so I've been playing around and found a function call schSymbolToPinList. This gives me what I want, however it gives a bit too much info. I only want a simple list like this:
I am able to use perl or similar script to fix this, but if SKILL can do this I'm interested to do this in one operation:)
cv=geGetEditCellView() ; or wherevertermDirMap=foreach(mapcar term cv~>terminals list(term~>name term~>direction))
Does that do what you want?
Hi Andrew, I try to get the accessDir of my different pin from my symbol cell. Because i try to create automaticelly a verilog file for creating a schematic decoder who use my logic cell. So i must to have the differents pins from my symbol and the direction ( left right top bottom) because i need the CORECT order of my pins => DVDDBIPBIP must to connect to DVDDDBIPBIP and not AB. Actually I use that for having the order => cv~>nets~>term~>name / but it's not the good order of my pins. When i create a symbol from my schematic i put some pins in the left list some pins in the right list... so the order pin is different and i think i could find the order if i find the pointer on this diffrent list ( left right...) but there is nothing in cv~>lpps~>shapes~>pin~>accessDir... so i don't understant how cadence manage the order to connect the pin when it use a verilog file. Do you know ?
module AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAATST_1_131(XBIPBIP, ABIP, AB, DVSSBIPBIP, DVDDBIPBIP);
input DVSSBIPBIP, DVDDBIPBIP;
AAA_COL1U1SRAM_ADD_DEC cell1( XBIPBIP, ABIP, AB, AB, AB, AB, AB, AB, AB, AB, AB, DVDDBIPBIP, DVSSBIPBIP );
AAA_COL1U1SRAM_ADD_DEC cell2( XBIPBIP, ABIP, ABIP, AB, AB, AB, AB, AB, AB, AB, AB, DVDDBIPBIP, DVSSBIPBIP );
In general it's best to connect to verilog by name (i.e. explicit connections) rather than by order. That way you don't need to worry about pin orders.
If the netlister is taking care of netlisting both the module and the instance (e.g. if it's an instance of a schematic), then the order doesn't really matter, because it will be consistent anyway.
If it is an instance of a textual view, and it is doing implicit connections (by order rather than by name), then the Verilog netlister would find:
cv=dbOpenCellViewByType("mylib" "mymodule" "functional")cv~>portOrder
and you might see: ("XBIPBIP<131:1>" "ABIP<11:2>" "AB<11:2>" "DVSSBIPBIP" "DVDDBIPBIP")
If you want to find out port directions (I think that's what you wanted rather than accessDir), then you'd use:
cv~>terminals~>name("XBIPBIP<131:1>" "ABIP<11:2>" "AB<11:2>" "DVSSBIPBIP" "DVDDBIPBIP")cv~>terminals~>direction("output" "input" "input" "input" "input")
The order of these two is the same. Note that it may not be the same as the order of the portOrder property though, AFAIK.
Looking the physical attributes of the pins (i.e. position etc) won't help you much I don't think. I don't believe accessDir is used on symbols (it's more for layout use, to restrict the direction that you can approach a pin from).