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List of symbol pin names and direction using SKILL

Tobben24

Hi,

I want to get a list of pins names and which direction the pins have from a symbol/schematic. I guess SKILL is the way to go? I new to SKILL, so if someone could push me in the right direction I would be grateful:)

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  • Andrew Beckett

    In general it's best to connect to verilog by name (i.e. explicit connections) rather than by order. That way you don't need to worry about pin orders.

    If the netlister is taking care of netlisting both the module and the instance (e.g. if it's an instance of a schematic), then the order doesn't really matter, because it will be consistent anyway.

    If it is an instance of a textual view, and it is doing implicit connections (by order rather than by name), then the Verilog netlister would find:

    cv=dbOpenCellViewByType("mylib" "mymodule" "functional")
    cv~>portOrder

    and you might see:  ("XBIPBIP<131:1>" "ABIP<11:2>" "AB<11:2>" "DVSSBIPBIP" "DVDDBIPBIP")

    If you want to find out port directions (I think that's what you wanted rather than accessDir), then you'd use:

    cv~>terminals~>name
    ("XBIPBIP<131:1>" "ABIP<11:2>" "AB<11:2>" "DVSSBIPBIP" "DVDDBIPBIP")

    cv~>terminals~>direction
    ("output" "input" "input" "input" "input")

    The order of these two is the same. Note that it may not be the same as the order of the portOrder property though, AFAIK.

    Looking the physical attributes of the pins (i.e. position etc) won't help you much I don't think. I don't believe accessDir is used on symbols (it's more for layout use, to restrict the direction that you can approach a pin from).

    Regards,

    Andrew.

Reply
  • Andrew Beckett

    In general it's best to connect to verilog by name (i.e. explicit connections) rather than by order. That way you don't need to worry about pin orders.

    If the netlister is taking care of netlisting both the module and the instance (e.g. if it's an instance of a schematic), then the order doesn't really matter, because it will be consistent anyway.

    If it is an instance of a textual view, and it is doing implicit connections (by order rather than by name), then the Verilog netlister would find:

    cv=dbOpenCellViewByType("mylib" "mymodule" "functional")
    cv~>portOrder

    and you might see:  ("XBIPBIP<131:1>" "ABIP<11:2>" "AB<11:2>" "DVSSBIPBIP" "DVDDBIPBIP")

    If you want to find out port directions (I think that's what you wanted rather than accessDir), then you'd use:

    cv~>terminals~>name
    ("XBIPBIP<131:1>" "ABIP<11:2>" "AB<11:2>" "DVSSBIPBIP" "DVDDBIPBIP")

    cv~>terminals~>direction
    ("output" "input" "input" "input" "input")

    The order of these two is the same. Note that it may not be the same as the order of the portOrder property though, AFAIK.

    Looking the physical attributes of the pins (i.e. position etc) won't help you much I don't think. I don't believe accessDir is used on symbols (it's more for layout use, to restrict the direction that you can approach a pin from).

    Regards,

    Andrew.

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