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How to import large verilog netlist into cadence schematic?

The verilog netlist contains more than 40 thousands component. When I import the netlist into cadence, it gives me an error of "Illegal bus reference - Can't tap "Neta" from "Netb".". I looked through the generated schematic, it messed up Neta and Netb. I cheked the Schematic Generation Options befoe importing the netlist again. The Maximum number of Rows/columns are limited to 1024. Is it possible to increase the Maximum Number of Rows/Columns of the schmatic before importing the large netlist?

Thanks,

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mliang over 12 years ago

Thanks very much. It is helpful. I will try it and to see what happens.
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mliang over 12 years ago

Thanks very much. It is helpful. I will try it and to see what happens.
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